標準元件庫特性化及混合臨界電壓元件庫設計

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姓名

邱奕瑋(Yi-Wei Chiu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

標準元件庫特性化及混合臨界電壓元件庫設計
(Standard Cell Library Characterization and Mixed-Threshold Voltage Cell Library Design)

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摘要(中)

隨著製程的進步，現有標準元件庫所使用的時間模型，將變得無法準確的來預估時間參數。在奈米電路設計時，電路非理想的效應變得愈來愈明顯，例如：IR Drop、訊號整合…等。以及在奈米低功率電路設計時，所使用到的低功率方法，例如：多種電壓供應、電壓島…等。上述的原因都會使得要讓現有的時間模型可以準確的模型化，而需要消耗非常多的時間來特性化多套的標準元件庫以增加準確度。然而，現今的EDA大廠已提出新的時間模型－電流源模型－來克服在奈米電路設計將會遇到模型準確度的問題，同時也不需要花費太多的時間在標準元件庫的特性化上。在本篇論文，我們找出新的時間模型的特性化方式，並將新的時間模型加入我們的標準元件庫的格式中。
現今高科技的生活中，可攜帶性的消費性產品的需求大大的增加。同時，在一件產品當中會將結合進許多功能的電路，例如：多媒體、通訊…等，以滿足消費者的需求。尤其是進步到奈米製程時，將會需要把許多功能的電路集中在一個小面積的單晶片系統中。這將會使得單位面積的功率消耗大大的增加，同時也使得由功率轉換成的熱大大的增加。熱對產品的可靠度是一個很大的挑戰。因此，功率消耗對於這些高科技的消費性產品變得相當的重要。功率消耗將會決定產品的使用期限、產品電池的大小及其使用時間的長短。在本篇論文中，我們提出一種低功率電路的設計方法。使用混合臨界電壓的方式，在不犧牲速度的情形下，達到低功率的電路設計。這種方式不需要額外增加電路的硬體，也不需要更改電路架構，即可達到低功率的需求。我們將此方法應用在標準元件庫的設計中，建立一套以混合臨界電壓方式來完成的標準元件庫。

摘要(英)

With the advance of process technology, the timing model in current standard cell library format becomes inaccurate when estimating the timing characteristics of circuits. In the nanometer circuit design, the non-linear effects of circuits become more and more obvious. For example, IR drop, signal integrity, etc. And in the nanometer low power circuit design, there are some low power techniques like multiple supply voltages, voltage islands, etc. The above reasons will make the current timing model become hard to maintain its accuracy and it will consume much time to characterize more sets of standard cell library to increase the accuracy. However, nowadays well-known EDA vendors have proposed new timing models called current source model to overcome above reasons and do not have to spend much time to characterize many sets of standard cell library. In this thesis, we find out the characterization flows of new timing model and add the new timing model in our standard cell library format.
In the modern high tech life, the demands for portable consuming products are increasing. Meanwhile, it has to combine many kinds of functions in a product to satisfy the requirements for consumers. For example, multi-media, communication, etc. Especially, with the process technology scaling down, designers have to put many functional circuits into a chip. This will make the power consumption in the unit area become greater and the heat transformed by power consumption increases largely. Heat is a challenge to the reliability of products. Therefore, the power consumption becomes very important for these high tech consuming products. It determines the useful life of the product, the size of battery and the period of useful time. In this thesis, we propose a low power design methodology using mixed-threshold voltage with staying the speed of circuits constant. Using this technique has neither to increase additional circuits nor to change the structure of circuits to obtain the requirement of low power. We apply this methodology to the establishment of standard cell library to create a mixed-threshold voltage standard cell library.

關鍵字(中)

★ 標準元件庫
★ 混合臨界電壓

關鍵字(英)

★ Mixed-Threshold Voltage
★ Standard Cell Library

論文目次

Chapter 1 Introduction 1
1.1 Introduction to Standard Cell Library 1
1.2 Deep-submicron Circuit Design Issues 3
1.3 Motivation and Goals 3
1.4 Thesis Organization 5
Chapter 2 Background Overview 6
2.1 Power Dissipation in CMOS circuits 6
2.1.1 Power Dissipation 6
2.1.2 Analysis of Power Dissipation in 130nm Process 7
2.2 Common Formats of Standard Cell Library 9
2.3 Brief Introduction to Liberty File 9
2.3.1 Classification of Power [5] [6] 12
2.3.2 Classification of Time 16
2.3.3 Create Look-up Table 18
2.4 Design of Standard Cell Library 20
2.5 Timing model of Nanometer Standard Cell Library 21
2.6 Summary 29
Chapter 3 Timing and Power Model Characterization Flow 30
3.1 Timing 30
3.1.1 Transition Time and Propagation Delay time 30
3.1.2 Input Capacitance 33
3.1.3 ECSM 34
3.2 Power 38
3.2.1 Internal Power 38
3.2.2 Leakage Power 39
3.3 Summary 40
Chapter 4 Low Power Standard Cell Library 41
4.1 Overview of Low Power Standard Cell Design Methodology 41
4.1.1 Multiple Threshold Voltage Circuit 42
4.1.2 Multiple Supply Voltage 48
4.2 Standard Cell Selection Rule 49
4.3 Design Flow 51
4.4 Cell Design 58
4.4.1 INV 61
4.4.2 3-input NAND 62
4.4.3 1-bit Half Adder 64
4.4.4 C17 65
4.5 Layout issue 66
4.6 Summary 68
Chapter 5 Conclusions 69
Reference 70

參考文獻

[1] MAGMA Design Automation, Inc. – Understanding ECSM and CCSM, http://www.magma-da.com/
[2] Liqiong Wei, Kaushik Roy, and Vivek K. De, “Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs,” VLSI Design, 2000. Thirteenth International Conference on 3-7 Jan. 2000, pp: 24-29
[3] Kiat-Seng Yeo and Kaushik Roy, Low-Voltage, Low-Power VLSI Subsystems, 1st ed. New York: McGraw-Hill, 2005.
[4] IEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks, IEEE Standard 1603TM-2003, 2004.
[5] Synopsys Corporation, Library Compiler User Guide: Modeling Timing and Power, 2004
[6] 郭建興, 標準元件庫特徵化程式使用者手冊 (User’s Guide of Characterization Utilities), 2003.
[7] Synopsys Corporation, Composite Current Source (CCS) Overview, Nov. 2004
[8] Effective current source model gains popularity: News from Cadence Design Systems, http://www.electronicstalk.com/news/cad/cad245.html
[9] Cadence Corporation, SIGNALSTORM NDC DATASHEET
[10] Cadence Corporation, SignalStorm Library Characterizer User Guide, Jul. 2004
[11] Synopsys Corporation, Open Source ECSM Format Specification Version 1.1, Dec. 2004, LibertyTM Extensions for ECSM
[12] S. Mutoh, et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS”, IEEE Journal of Solid-State Circuits, vol.30, no.8, pp. 847-854, 1995.
[13] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, J. Yamada, “A 1-V high speed MTCMOS circuit scheme for power-down applications”, IEEE J. Solid-State Circuits, vol.32, pp. 861-869, Nov. 6, 1997.
[14] H. Kawaguchi, K. Nose and T. Sakurai, “A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current”, IEEE International Solid-State Circuits Conference, 1998, pp. 192-193.
[15] Liqiong Wei, Zhanping Chen, Roy, K., Yibin Ye, De, V., “Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications” Design Automation Conference, 1999. Proceedings. 36th, Jun. 1999, pp. 430-435.
[16] Frank Sill, Frank Grassert, and Dirk Timmermann, “Low Power Gate-level Design with Mixed-Vth (MVT) Techniques,” Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium, Sep. 2004. pp. 278-282.
[17] Neil H. E. Weste, David Harris, CMOS VLSI DESIGN – A Circuit and System Perspective,” 3rd ed., Addison Wesley, 2004.
[18] Website Chip123, 靜態時序分析（Static Timing Analysis）基礎及應用, 陳麒旭.
[19] “Standard Cell Characterization”, Richard Sohnius, 16.12.2003
[20] TSMC 0.13um (CL013G) Process 1.2-Volt SAGE-XTM Standard Cell Library Databook, Release 2.5, June 2002
[21] EETimes.com-ECSM sets new standard for timing model accuracy

指導教授

劉建男、周世傑
(Chien-Nan Liu、Shyh-Jye Jou)

審核日期

2006-7-18

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