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姓名 洪國源(Kuo-yuan Hung) 查詢紙本館藏 畢業系所 電機工程學系在職專班 論文名稱 Band解法器與BILU解法器應用於三維元件模擬之整合
(Integration of Band Solver and BILU Solver for 3-D Device Simulation)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 在三維的元件模擬中,傳統的分解法產生大量的非零項,它會消耗大量的記憶體空間。然而個人電腦的記憶體空間有其限制而且三維元件的立方體數也將會被限制。因此,在此篇論文中,我們提出了整合型帶狀不完全LU分解法與帶狀LU分解法的模擬器,它可改善記憶體空間不足的問題。我們透過三維的p-n diode來驗證這兩種分解法,並且提出兩種解法器的特性與差異。依據這兩種分解法的特性,我們可選擇合適的解法器來應用在不同的三維元件結構,使得我們的個人電腦能在三維元件特性模擬中發揮最大效能,達成節省記憶體空間的目的。我們也模擬了不同結構的MOSFET,進一步地分析與探討三維MOSFET的特性。 摘要(英) In 3-D device simulation, there will have a lot of nonzero items in matrix solver and cost many memory space. However, the memory space has its limitation and the number of cubic grids will also be confined. In this thesis, we propose the integration matrix solver using Banded incomplete LU method and Banded LU method. The integration solver improves the problem that the memory space is insufficient. We use 3-D p-n device to verify our simulator and find out the feature between the two solvers. Based on the solver property, we select the suitable solver for corresponding 3-D structure. After that, our simulator can save the memory space and make our personal computer working effectively. Finally, we run the simulation of MOSFET in 3-D different structures to analyse the device characteristics. 關鍵字(中) ★ 邊界不完全LU分解法
★ 三維元件模擬關鍵字(英) ★ 3-D device simulation
★ BILU Solver論文目次 1. Introduction 1
2. Band Solver and BILU Solver for 3-D Model 2
2.1 3-D Equivalent Circuit Model 2
2.2 3-D Band Matrix Solver 6
2.3 3-D Banded Incomplete LU Solver 12
3. Integration of Banded LU Solver and BILU Solver in 3-D
Simulation 16
3.1 Introduction to the Integration Method 16
3.2 3-D Device Simulation 21
3.3 Comparison of BILU Solver and Banded LU Solver 25
4. Applications of 3-D MOSFET Simulation 29
4.1 Simulation of MOSFET Characteristics 29
4.2 The Triple-gate MOSFET Simulation 32
4.3 MOSFET Simulation of Dimension modulation 38
5. Conclusion 42參考文獻 Reference
[1] C. C. Chang, C. H. Huang, J. F. Dai, S. J. Li, and Y. T. Tsai, “3-D numerical device simulation including equivalent-circuit model,” IEDMS, 2002.
[2] P. C. H. Chan and C. T. Sah, “Exact Equivalent Circuit Model for Steady-state Characterization of Semiconductor Devices with Multiple-Energy-Level Recombination Centers,” IEEE Transactions Electron Devices, vol. ED-26, no. 6, pp.
924-936, 1979.
[3] K. Mayaram and D. O. Pederson, “Coupling Algorithms for Mixed-Level Circuit and device Simulation,” IEEE Transactions on Computer-Aided Design, vol. 11, no.8,
1992.
[4] J. Vlach and K. Singhal, “Computer methods for circuit analysis and design,” Van Nostrand Reinhold, 1994.
[5] J. F. Dai, “Development of 2-D and 3-D Numerical Device Simulator including an Improved L-ILU Solver and the Circuit representation of PDM,” Ph.D. dissertation,
2004.
[6] L. W. Nagel, “SPICE2：A computer to simulate semiconductor circuit,” Univ.
California Berkeley, ERL Memo ERL-M520, 1975.
[7] Y. Jin, C. Zeng, L. Ma, and D. Barlage, “Analytical threshold voltage model with TCAD simulation verification for design and evaluation of tri-gate MOSFETs,” Solid-State Electronics, 2007.
[8] W. Chen, Y. Taur, D. Sadana, K. A. Jenkins, J. Sun, and S. Cohen, “Suppression of the SOI floating-body effects by linked-body device structure,” VLSI Technol, p. 92,1996.
[9] D. Suh and J. G. Fossum, “Dynamic floating-body instabilities in partially depleted SOI CMOS circuits,” IEDM Tech. Dig., p. 661, 1994.
[10] Y. T. Yeow and C. H. Ling, “Teaching Semiconductor Device Physics with Two-Dimensional Numerical Solver,” IEEE Transactions on Education. vol. 42, no.1, 1999.指導教授 蔡曜聰(Yao-Tsung Tsai) 審核日期 2008-6-27 推文 plurk
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