以FPGA實現DVB-T/H系統之二維一維與AGC-CR通道等化技術

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姓名

林家禾(Jia-he Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以FPGA實現DVB-T/H系統之二維一維與AGC-CR通道等化技術
(FPAG Realization of AGC-CR and 2D/1D Channel Equalization Techniques for DVB-T/H OFDM System)

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摘要(中)

目前在台灣，數位電視廣播系統的規格有應用於固定式接收的DVB-T與適用於移動式接收的DVB-H。在DVB-T/H的系統中，為了補償符碼通過通道時的失真，我們會在接收端使用頻域等化器的設計。在傳統上通道估測是依據訓練樣本來訓練頻域等化器的係數，然後再使用一維的內插技術來估測其他子通道。而在移動式的環境中，我們會使用傳統的通道估測以及二維的內插技術來追蹤因接收端的移動所造成的通道變化。
另外一種等化技術是以LMS演算法為基礎，將頻域等化器之係數收斂到最小誤差。然而LMS演算法的收斂條件需要針對每個子通道來求得適當的Step-size，當子通道數目增加時，Step-size求得將會非常繁雜且收歛速度不一。因此，我們提出一套基於自動增益控制與載波回覆概念之改進的頻域等化器演算法。此頻域等化器可使每個子通道係數在相同且單一的Step-size參數下，能夠快速收歛並且具有良好的通道雜訊抵抗能力。最後，我們提出一套以CORDIC為基礎的頻域等化器電路架構。在傳統的通道估測需要乘法以及除法器來計算等化器的係數，而以CORDIC為基礎的頻域等化器則只需要加法器便可計算等化器的係數。本論文將會討論各種應用於DVB-T/H系統的等化技術的理論與模擬，以及在FPGA上實現的結果比較。

摘要(英)

Presently Digital Video Broadcasting standard has immobile Terrestrial(DVB-T) and
mobile Handheld (DVB-H) in Taiwan. For removing the multi-path channel effects, a frequency
domain equalizers is usually employed in the receiver. Conventionally, the subchannel responses
are estimated by using known training sequence for channel estimation. Then one-dimension
interpolation techniques are used to calculate the channel responses or the equalizer coefficients
of other sub-tones. In mobile environment we use conventional channel estimation and twodimension
interpolation techniques for tracking the channel variation with mobile receiver.
An alternative equalization technique is to base on the LMS algorithm for converging the
coefficients of FEQ to the minimum error. But it needs to compute proper step-size for each
sub-channel to satisfy convergent rule. Besides, convergent speeds of all sub-channels will not be
all the same while the conventional LMS algorithm is applied, especially when the sub-channel
number is large. According to this reason we propose an improved equalization algorithm based
on automatic gain control and carrier recovery techniques. This algorithm needs only single
step-size for all sub-channels to have high and almost equal convergent speed and resistant
ability to the channel effect. Finally we propose an equalization algorithm based on CORDIC.
In conventional channel estimation we need multiplication and division for estimate equalization
coefficients. But with the proposed equalization based on CORDIC we may estimate equalizer
coefficients by adders. In this thesis we will discuss the theory, similation and FPGA emulation
of several equalization techniques applied in DVB-T/H system.

關鍵字(中)

★ 應用於數位電視廣播系統之頻域通道等化技術

關鍵字(英)

★ FEQ techniques for DVB-T/H system

論文目次

Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . 1
1.2 Theisis Organization . . . . . . .. . . . . . . . 2
Chapter 2 OFDM System and DVB-T/H Standard 3
2.1 OFDM System . . . . . . . . . . . . . . . . . . . 3
2.1.1 Multi-carrier Modulation System . . . . . . . . 3
2.1.2 DFT/IDFT concept .. . . . . . . . . . . . . . . 4
2.2 DVB-T/H Standard . . . . . . . .. . . . . . . . . 7
2.2.1 Transmission Parameters . . . . . . . . . . . . 7
2.2.2 Cyclic Prefix . . . . . . . . . . . . . . . . . 7
2.2.3 Reference Signal . . . . . .. . . . . . . . . . 9
Chapter 3 Frequency-Domain Equalizer in DVB-T/H System 12
3.1 FEQ System . . . . . . . .. . . . . . . . . . . . 12
3.2 Channel Estimation . . . . . . . . . . . . . . . 14
3.3 Interpolation . . . . . . . . . . . . . . . . . . 16
3.3.1 Piecewise Linear Estimation . . . . . . . . . . 16
3.3.2 Gaussian Estimation . . . . . . . . . . . . . . 17
3.3.3 Cubic-Spline Estimation . . . . . . . . . . . . 17
3.3.4 Parabolic Estimation . . . . . . . . . . . . . 18
3.3.5 Wiener Filter Estimation . . . . . . . . . . . 18
3.4 Channel Estimation with 1-D and 2-D Interpolation 19
3.4.1 1-D Interpolation with Pilot Tone . . . . . . . 20
3.4.2 2-D Interpolation with Pilot Tone . . . . . . . 24
3.5 Auto Gain Control Carry Recovery . . . .. . . . . 26
3.5.1 Conventional Adaptive FEQ with LMS Algorithm . 26
3.5.2 Concept and Algorithm of AGC-CR Based FEQ . . . 28
3.6 CORDIC Channel Equalization . . . . . . . . . . . 30
3.6.1 Concept . . . . . . . . . . . . . . . . . . . . 30
3.6.2 Rotation mode . . . . . . . . . . . . . . . . . 30
3.6.3 Vectoring mode . . . . . . . . . .. . . . . . . 33
3.6.4 Frequency Equalization with CORDIC Vectoring mode 34
Chapter 4 Simulation and Implementation 38
4.1 Simulation Background . . . . . . . . . . . . . . . .. . . . . . 38
4.2 1-D and 2-D Interpolation . . . . . . . . . . . . . . . . . . . . 38
4.3 AGC-CR . . . . . . . . . . . . . . . . . . . . . 40
4.4 CORDIC . . . . . . . . . . . . . . . . . . . . . 40
4.5 FPGA Results . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 5 Conclusion and Future work 45
Bibliography 46

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指導教授

薛木添(Mu-tian shiue)

審核日期

2007-7-24

推文