本論文利用0.35 um CMOS及0.18 um CMOS標準製程實現光檢測器。首先在0.35 um CMOS光檢測器部分，設計目的在於改善矽(silicon) 光檢測器(PD)響應度普遍不高的情形，針對元件佈局的變化設計六邊形及八邊形的光檢測器，藉由佈局的變化能在有限面積下增加響應度。其中以六邊形光檢測器特性最好，響應度在逆偏壓14 V時達到0.12 A/W，可以改善傳統直條狀PD的響應度約1.27倍。 此論文第二部份為0.18 um CMOS光檢測器部分，使用n型、p型井製程及離子佈值製作光檢測器元件，並且加入自行設計的體架構(Body Contact)對CMOS光檢測器頻寬改善。當外加偏壓至體架構時，在光檢測器的下方會形成一電流路徑而有效消除慢速擴散載子，得以增加光檢測器頻寬及速度。而所設計的光檢測器中，將體架構環繞在元件外圍並且在內部交趾分布的結構頻寬表現最好。當體架構偏壓為10 V時，可得到頻寬由1 GHz改善至1.5 GHz。結果顯示：一、加入體架構偏壓時，光檢測器下方的電流後可以掃除慢速擴散載子，因此光檢測器的頻寬得以提升；二、比較不同設計的體架構，對於掃除慢速擴散載子效果會有差異，完整的外圍環讓體架構電流可以形成更完整的橫向電流面，對於元件頻寬提升效果較明顯。 論文最後為利用0.18 um CMOS製程，將光檢測器(PD)、轉阻放大器(Transimpedance)及限制放大器(Limiting Amplifier)整合成前端光接收器，實現差動(Differential)以及單邊(Single-end)電路架構的850 nm光接收器，但轉阻放大器緩衝級偏壓設計考慮未周詳，因此產生了低頻震盪的問題。論文中也有提出解決得方法，差動架構光接收器功率消耗為124 mW，可得轉阻增益ZT約為49 dB、3 dB頻寬為2.2 GHz以及光電轉換頻寬為1.5 GHz的電路。單邊架構光接收器可得轉阻增益ZT約為52 dB、3 dB頻寬為1.4 GHz以及光電轉換頻寬為1 GHz的電路。 This work demonstrates photodiodes (PDs) fabricated by standard silicon process technologies. Two kinds of PDs are proposed. One is in 0.35 um CMOS technology and the other is in 0.18 um CMOS technology. This first section is the design of a high responsivity PD, and the PD layout is hexgon and ocagon in 0.35 um CMOS technology. The main ideas behind the layout design are to in crease the sidewall depletion region by fractal geometries. We show a good PD responsivity, the measured of the hexagon PD is 0.121 A/W and -3 dB bandwidth 790 MHz. The second section is the design of a high bandwidth PD in 0.18 um CMOS technology. We remove the slow diffusion carries which are generated from substrate in CMOS PD by using body contact design with supplied voltage to curries into ground and improving PD bandwidth. When Body voltage is 10 V, the PD shows a much higher electrical bandwidth of 1.5 GHz. In final section, we try to combine the Regulated Cascode Transimpedance amplifier (RGC TIA), Limiting amplifier(LA), and the previous available photodiode in Silicon (Si) CMOS technology to realize a high speed and highly integrated photoreceiver, which is fully compatible in standard Si CMOS process. Using Regulated Cascode Transimpedance amplifier at input can reduce effect of capacitance on PD and PAD. However, the voltage of the buffer stage is not considered carefully, hence the circuit gets a wrong current. The measured -3dB bandwidth of the differential and single-end circuit are about 2.2 GHz, and 1.4 GHz respectively, while their gain are about 49 dB and 52 dB.Implemented in a 0.18 um CMOS technology, the total power dissipation is 124 mW and 50.9 mW. The chip size is 0.6 mm2 and 0.576 mm2.
