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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/2200


    Title: 以FPGA為基礎剛性攻牙控制IC之研製;Design and Implementation of an FPGA-based IC for Rigid Tapping
    Authors: 楊學之;Hsueh-Chih Yang
    Contributors: 機械工程研究所
    Keywords: 剛性攻牙;積體電路設計;現場可開發邏輯閘陣列;Rigid Tapping;IC Design;FPGA
    Date: 2002-07-03
    Issue Date: 2009-09-21 11:40:42 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 以FPGA為基礎剛性攻牙控制IC之研製 研究生:楊學之 指導教授:董必正 教授 國立中央大學機械工程學系 摘要 本論文以可程式邏輯閘陣列(FPGA)實現可應用於CNC工具機進階功能之剛性攻牙控制的泛用型控制IC,此控制IC包含馬達控制電路、整合PC介面電路、光編碼器電路、馬達驅動訊號電路、D/A介面電路、ISA介面電路與FPGA programming 電路,採高度模組化設計,利用全球通用且跨平台之VHDL硬體描述語言設計。所研製的控制IC具有可程式化的特點,經由相關控制暫存器的設定,即可完成剛性攻牙主軸與Z軸的控制。控制器模組包含位置迴路控制,位置迴路採用具有前饋路徑的比例積分控制架構,取得主軸位置後與Z軸的回授訊號作比較,經由控制器的計算後將控制命令送至Z軸伺服馬達驅動器,控制之命令型態為電壓命令,取樣頻率則為10KHz。此控制IC實現約使用五千個閘數量的FPGA資源,在IC設計驗證方面,本文除了進行硬體電路模擬外,另藉由一組自行設計的D/A介面電路實驗驗證此控制IC的特性,實驗結果顯示所研製的控制IC具有預期的控制性能,且設計的功能皆能正常運作。 Design and Implementation of an FPGA-based IC for Rigid Tapping Student: Hsueh-Chih Yang Advisor: Dr. Pi-Cheng Tung Department of Mechanical Engineering National Central University Abstract This thesis presents the design and implementation of a universal Rigid Tapping control IC using Field Programmable Gate Array (FPGA). The Rigid Tapping is one advanced function of the CNC machine tool. The proposed control IC consists of motor control circuit, PC interface circuit, photo encoder circuit, motor driver circuit, ISA interface circuit and FPGA programming circuit with module design. VHDL will be used to design the IC. The IC which was designed and implemented features of programmability, and we can set the related control registers to control the spindle and Z-axis under Rigid Tapping. The controller accomplishes position loop control. Proportional and integral with feed-forward control is adopted in position loop. Decoding the spindle motor’s position we compare it with the position of Z-axis. The controller will calculate the command and sent the voltage command to the servo motor driver of Z-axis. The sampling rate is 10KHz. Five thousand of the FPGA typical gates were used to realize the proposed control IC. In this thesis, software simulation and a D/A interface circuit have been carried out to verify the functions of the control IC. Experimental results show that the control IC has the control capability and feasibility expectedly and all the designed functions can work correctly.
    Appears in Collections:[機械工程研究所] 博碩士論文

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