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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/3159

    Title: 奈米尺度多孔矽製作絕緣層矽晶材料之研究;Study in nano-scale porous silicon fabrication for silicon-on-insulator materials
    Authors: 周欣麟;Xin-Lin Zhou
    Contributors: 機械工程研究所
    Keywords: 多孔矽;電化學蝕刻;electrochemical etching;porous silicon
    Date: 2009-07-03
    Issue Date: 2009-09-21 12:07:24 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 在這半導體製程越來越進步的時代,為了遵循摩爾定律(Moore’s Law),絕緣層矽晶(Silicon on insulator, SOI)材料結構成為半導體製程進入奈米尺度所面臨的漏電流效應難題最佳解決材料。目前常見製作絕緣層矽晶材料的方法為Smart-Cut®製程,利用高劑量氫離子佈植於矽晶圓內,再經晶圓鍵合製程與高溫退火處理,使氫離子聚集產生剝離以達到薄膜轉移之目的。 本論文研究之目地為使用電化學蝕刻方式製作一深埋多孔矽層,在特定蝕刻參數下,以電化學蝕刻重掺雜之P型矽晶圓,產生溶解反應生成多孔層,此多孔層會產生裂縫區,並可以在後續製程上利用一小應力造成上方薄膜沿著裂縫產生剝離,達到薄膜轉移之目的,此薄膜轉移方法可以應用在絕緣層矽晶材料製作上。 Even with the mature semiconductor processing technology, the Moore’s Law is difficult to keep up with the necessity. The Silicon on Insulator (SOI) has become a material to solve the leakage effect when the process is in the scale of nanometer. Recently, Smart-Cut® is a common means for manufacturing the SOI. By applying the high dosage of hydrogen ions and implanting them into the silicon wafers, followed with wafer bonding process and high temperature annealing, the hydrogen ions gather and finishe the purpose of layer transfer. This thesis is in reference to fabricating a buried porous silicon layer under a capping silicon layer by using electrochemical etching. With certain parameters, the heavily doped P-type silicon wafer is etched by electrochemical method to cause the dissolving reaction and produce the porous layer. Under the capping silicon layer, Crevices are existent in the porous layer. In the later process, a small stress is applied on the creviced zones to cause the layer split along the crevices. It provides another approach to fabricate SOI material by using this method.
    Appears in Collections:[機械工程研究所] 博碩士論文

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