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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/3861


    Title: 銅覆晶墊層銲點界面之電遷移失效模式研究;Study of EM(Electromigration) failure modes at Sn/Cu cathode interface in Flip-chip solder joint
    Authors: 莊曜群;Yao-Chun Chuang
    Contributors: 化學工程與材料工程研究所
    Keywords: 覆晶封裝;界面反應;電遷移;無鉛銲料;Pb-free solder;Electromigration;interfacial reaction;Flip-chip
    Date: 2008-06-04
    Issue Date: 2009-09-21 12:24:29 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 微電子封裝工業目前大量的以錫球銲接的方式,將電子之元件晶片連接到印刷電路板上( Printed Circuit Board, PCB )。這些銲點組裝後的性質直接會影響封裝後整體晶片元件的可靠度。為容納更高密度的I/O(Input/Output)數目在IC的晶片上,未來覆晶的金屬墊層(pad)與銲料凸塊(solder bump)尺寸將大幅縮小。如此,每個銲料凸塊所承受的電流密度,會因此快速增加,而造成電致遷移效應,此效應會導致凸塊接點的失效;所以電遷移效應將嚴重威脅高功能及高密度IC晶片之可靠度,這是急需解決的重要課題。再加上通過銲點之電流密度將高達104 A/cm2。電遷移效應目前已經對銲點的可靠度造成影響,兩種主要失效模式被發現。第一種失效模式為電遷移效應中最典型的一種。經過一段時間的通電後,無論是塊材(bulk)或是薄膜(film)於陰極端都會產生明顯的質量損失,而形成孔洞(void)。第二類失效模式為受電遷移效應而誘發陰極端導線或金屬墊層產生溶解的現象。 此論文以實驗與理論的印證,完整的探討銅覆晶墊層銲點的失效模式,用理論與實驗討論各層的銅原子通量,並且估計各層銅通量隨著電流密度與溫度的變化來解釋在銅覆晶銲點界面所發生的各種失效模式,最終利用估算的原子通量描繪出一失效地圖,此圖可用來預測在任意電流密度與溫度條件下的失效模式,對於如何設計出一可靠度高的銅銲點,提供很重要的資訊。 第二章中,我們針對錫銅覆晶銲點進行不同溫度及不同電流密度的電遷移測試實驗,並利用實驗的數據獲得: (1) 估算出銅箔消耗的動力學模式 (2) 在固定電流密度下,發現溫度將改變電遷移失效模式,以及陰極的界面銅箔消耗模式與介金屬化合物的生成 (3) 在固定溫度的實驗中,我們發現改變電流密度對銅箔失效與界面金屬化合物生長機制的影響。 第三章討論電遷移效應對界金屬化合物的影響,綜合過去電遷移的研究,介金屬化合物的電遷移性質都被忽略了,我們以液態電遷移方法(liquid-electromigration)成功的製備結晶性良好的錫銅化合物(Cu3Sn and Cu6Sn5),並進行Cu6Sn5的電遷移測試。第四章中我們詳細討論在錫銅覆晶銲點中的各層銅原子通量,利用銅原子通量建立出電遷移效應對於錫銅銲點的失效機制,合理的解釋出在第二章所觀察到的電遷移現象。最終在第五章中,我們利用討論出的失效機制描繪出一失效地圖。 As the speed and function of the CPU continuous to increase, I/O count (Input-Output) also increases dramatically. According to the semiconductor roadmap, by 2007 the current density for each C4 solder bump will exceed 104 A/cm2. Two EM failure modes have been reported. The first one is voiding, which occurs at the solder/compound interface. The second EM failure mode is the EM-induced dissolution of the Cu metal bond pad or the Cu trace lines. The current density and the stressing temperature are the critical parameters for various EM failure modes. We found that the critical EM parameters, the current density and the stressing temperature, significantly influence various EM failure modes, for example, Cu consumption, voids formation and asymmetric interfacial compound formation in our experimental results. From the experimental results in this study, we build up a detail mechanism of EM effect on flip-chip Cu/Sn solder joint by analyzing the Cu atomic flux step by step. EM-induced Cu consumption, voids formation, and asymmetric interfacial compound formation can be well-defined and explained by this mechanism. Finally, we can define Z* of Cu in the Sn matrix is around 130 and establish a map for EM failure mode. The failure map is of important to those who design the flip-chip joint structure with an excellent reliability. In chapter 2, we investigate the Cu/Sn interface of flip-chip solder joints under current stressing. From the experimental results with different current densities at different temperatures, we find out the critical factors influence on flip-chip Cu/Sn solder joints and obtain important parameters for calculating EM flux. In chapter 3, we successfully fabricate crystalline Cu3Sn and Cu6Sn5 bulk compounds by liquid-electromigration method. Also, we observe EM effect on the Cu6Sn5 compound. Then, we discuss the detail mechanism of EM effect on Sn/Cu flip-chip solder joint and show how the atomic flux be calculted in every step in chapter 4. Moreover, voids formation, EM-induced Cu consumption, and asymmetric IMC formation can be well-defined by the equating atomic fluxes. Finally, we can define Z* of Cu and establish a failure map for EM failure mode in chapter 5.
    Appears in Collections:[化學工程與材料工程研究所] 博碩士論文

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