| 摘要: | 隨著元件尺寸持續縮小，一維的金屬線與金屬線矽化物由於在半導體奈米元件的金屬接點與內連線中具有應用的潛力而逐漸受到重視。因此本研究特別著重於以陽極氧化鋁模板(Anodic Aluminum Oxide, AAO)法結合電鍍技術製備大面積規則排列鈷金屬奈米線陣列，及不同溫度熱處理下鈷金屬與(001) Si之界面反應。 在本實驗中，將利用一有效的陽極氧化鋁模板製程技術，製作出尺寸可控制調變的鈷金屬奈米線。而在實驗中藉由控制電解條件，以適當的電解液中進行處理後，可成功將高純度鋁片製備成有規則排列之孔洞，且孔洞尺寸可調的陽極氧化鋁結構。以電鍍法在奈米孔洞通道中鍍製鈷金屬並移除陽極氧化鋁模板後，便能獲得不同奈米尺度的多晶結構之鈷金屬奈米線。 將奈米尺寸的鈷金屬線滴置在(001) Si基材上經400 ℃ 30分鐘熱處理，可發現試片中主要生成相為CoSi並伴隨有Co2Si相存在。而當溫度提高到500 ℃時，在電子選區繞射(SEAD)圖中發現有CoSi2的繞射環，顯示具有低電阻的CoSi2在此時已開始生成，且其中有部分的CoSi2已形成磊晶結構。CoSi2與(001) Si基材之磊晶關係經鑑定為 [001] CoSi2 // [001] Si and (200) CoSi2 // (400) Si。再將熱處理溫度提升到600 ℃或更高時，在試片中可觀察到奈米線已完全反應形成CoSi2相。然而在高溫熱處理後鈷矽化物的形態出現明顯的聚縮，這些刻面結構在高溫退火後聚縮情形更為明顯。根據TEM與SEAD分析，可鑑定得這些在 (001) Si表面形成磊晶CoSi2奈米線的刻面為倒金字塔的形狀，並且每個點狀的CoSi2角錐體是由一個(001)表面與四個{111}的界面所構成。 As the device dimensions continue to scale down, one-dimensional (1-D) metal and metal silicide nanowires have attracted much attention due to their potential applications as metal contacts and interconnections in the semiconductor nanodevices. Therefore, in this study, particular emphases are focused on the synthesis of large-area, well-aligned cobalt metal nanowire arrays by using the electrodeposition in conjunction with anodic aluminum oxide (AAO) templates technique, and the interfacial reactions between the produced Co metal nanowires and (001)Si substrates after different heat treatments. To fabricate the size-tunable Co metal nanowire arrays, an effective technique－anodic alumina oxide (AAO) template-mediated process were utilized in the present study. Under controlled anodization conditions, self-ordered, pore-size tunable AAO templates were successfully fabricated by anodization of high-purity aluminum sheets in appropriate acid solutions. After electrodeposition of Co metal into the nanochannels and subsequent removing the AAO templates, a series of polycrystalline Co metal nanowires of different diameters were obtained. For the nanoscale Co wires on (001)Si samples annealed at 400 ℃ for 30 min, Co2Si phase was found to coexist with the dominant ploycrystalline CoSi phase. With increasing the annealing temperature to 500 ℃, diffraction rings corresponding to the CoSi2 phase were found in the selected area electron diffraction (SAED) pattern, showing that low-resistivity CoSi2 starts growing in the samples. In addition, some of the CoSi2 were found to grow epitaxially. The crystallographic relationship of epitaxial CoSi2 phase with respect to (001)Si substrate was identified to be [001]CoSi2 // [001]Si and (200)CoSi2 // (400)Si. Further annealing at 600 ℃ or above, CoSi2 phase was found to completely form in the samples. However, morphological degradations of Co silicide nanowires were evident in the higher temperature annealed samples. The faceted structures were found to be more prone to form at higher temperatures. Based on TEM and SAED analysis, the faceted structures of epitaxial CoSi2 nanowires formed on (001)Si was identified to be an inverse pyramid in shape, and each pyramidal-shaped CoSi2 dot was composed of one (001) surface and four {111} interfaces. |
