Cu-Sn-Cu覆晶結構之陰極銅箔消耗與電遷移失效模式; Flip-Chip Cu Pad Consumed at the Cathode Side and Electromigration (EM) Failure Modes

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Title:	Cu-Sn-Cu覆晶結構之陰極銅箔消耗與電遷移失效模式;Flip-Chip Cu Pad Consumed at the Cathode Side and Electromigration (EM) Failure Modes
Authors:	廖珮嵐;Pei-lan Liao
Contributors:	化學工程與材料工程研究所
Keywords:	失效模式;覆晶;電遷移;flip-chip;electromigration;failure modes
Date:	2007-06-21
Issue Date:	2009-09-21 12:28:07 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	使用Cu/Sn/Cu覆晶式結構研究，觀察電遷移效應下，於不同電流密度對陰極銅箔消耗、界面的介金屬化合物之影響，實驗溫度分別為125、100與80℃，電流密度的範圍在1~6×103A/cm2通過Cu/Sn/Cu試片進行通電實驗，4天後，經電遷移效應，陰極端銅箔消耗與電流密度成一次方正比的關係，得到修正的銅箔消耗動力學關係式為Δh=Bexp( )tnj，藉由此式，可預估不同電流密度下，陰極銅箔消耗的情形。此外，於低溫55 ℃，電流密度約5.5×103 A/cm2通過試片10天，陰、陽極兩端觀察到不同的現象，電子流入端，銅箔消耗非常的嚴重，另一端，也是遠離電子流入端，孔洞在IMC(介金屬化合物)/solder界面的銲料中形成，而陽極端，Kirkendall voids於Cu3Sn/Cu界面被發現，陰極Cu3Sn/Cu界面則無觀察到。 To study electromigration (EM), flip-chip Cu-Sn-Cu structures were prepared. This study investigates on effect of current density induced Cu pad consumption at the cathode side and interfacial metallic compound. EM test were carried under three temperatures, which are 80, 100 and 125 ℃ for 4 days, respectively. Current densities were 1~6×103 A/cm2 passed through the solder bumps. After EM test, the Cu consumption increased with current density linearly. Therefore, we modified kinetics of the Cu consumption equation as Δh=Bexp( )tnj. By this expression, the Cu consumption will be predicted under any current density. Besides, Solder bump were under 5×103 A/cm2 at 55 ℃ for 10 days. Different phenomenons were observed at the both side. Cu pad consumed very seriously at the current entry point. On another corner which distant from the current entry point, voids formed at the IMC/solder cathode interface. At the anode side, the Kirkendall voids were found to occur at the anode Cu3Sn/Cu interface. No Kirkendall voids found at the cathode side.
Appears in Collections:	[National Central University Department of Chemical & Materials Engineering] Electronic Thesis & Dissertation

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