English  |  正體中文  |  简体中文  |  Items with full text/Total items : 69937/69937 (100%)
Visitors : 23225021      Online Users : 464
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/42577

    Title: 鍺量子點元件之研製與物理分析---子計畫三:鍺量子點元件特性之理論模擬(I);Theoretical Investigation of Optical and Transport Properties of Germanium Quantum Dot Devices(I)
    Authors: 郭明庭
    Contributors: 電機工程系
    Keywords: 材料科技;物理類
    Date: 2005-07-01
    Issue Date: 2010-11-30 17:02:28 (UTC+8)
    Publisher: 行政院國家科學委員會
    Abstract: 主計畫展現獨特且實際的提案來推動精藝的鍺量子點室.單電子電晶體製作。本計畫三個各別計晝主持人,李佩雯教授,洪志旺教授及郭明庭教授,將共同努力達成此計晝的目標。在這子計晝,第一年的目標是計算出鍺量子點的電子能階與電子電子交互作用力。第.年利用Keldysh 格林函數法及Anderson 模型來建立流經鍺量子點的電流,其中並運用穩定法來決定穿隧率的大小以便求得實際電流。第三年鍺量子點的室 .單光子產生器的自發性譜線是主要研究課題。在這子計晝我們利用(1)緊束縛法結合波意鬆方程來計算量子點的電子能結構,同時亦考慮微數電子交作用對電子能的重整,以便瞭解電子能結構和量子點大小關係。並確立鍺量子點在何種奈米尺度下足以產生足夠大的電苛斥位能(Charging energy) 來克服溫度效應對電流.益的破壞。此模擬也可以讓我們理解鍺在奈米尺度介電常數和塊材時的介電常數有何不同。 (2)利用Keldysh 格林函數方法與Anderson 模型來計算(a)單電子電晶體的穿隧電流如何被閘極電壓及汲極電壓調變(b)建立可靠的方法求解量子點與各別電極間的穿隧率,進而瞭解二氧化矽的厚度與穿隧率的關係。以便用最薄的.氧化矽層製作最小體積的室溫單電子電晶體。此薄的高位勢障的二氧化矽層也將是室溫單光子產生器能否實現的關鏈之一。 (3)計算鍺量子點的吸收與放射譜線的強度與分佈,以便對exciton, trion 及biexciton 所對應的譜線位置進一步確認 ,以利共振腔大小的設計進而決定出所需的單光子類型。同時檢驗Purcell 效應對自發性放射率的放大與壓制效果。精密的exciton, trion 及 biexciton 譜線量測,可以用來理解費米子在零維度的二體,三體及四體問題。 Main proposal presents a unique and realistic program focused upon pushing the state-of- the- art in the fabrication of germanium quantum dot single electron transistors (Ge SETs) operating at temperature 300 K. Three investigators in main proposal, Prof. P. W. Li, J. W. Hong, and David. M. T. Kuo, will undertake the task of realizing this shared common goal and version. In this subproposal the focus of the first objective is to calculate the electronic structure of Germanium (Ge) QDs embedded in 2 SiO . To model the transport properties of the Ge single electron transistors (SETs) with dc or ac electrical field at room temperature is the focus of the second objective . Finally we will also model the emission spectrum of single Ge QD embedded in a pn junction with Keldysh Green function and realistic effective mass model. The reliable numerical calculation (tight binding including micro-strain) incorporated with Poisson equation is used to calculate the electronic structure of Ge quantum dots (QDs) and electron-electron interaction (Charging energy) as a function of quantum dot radius for different numbers of electrons in dot. Because the size of Ge QD studied is few nm scale, atomic scale approach could provide a reliable calculation. The tunneling current of Ge SETs as functions of temperature, gate voltage and bias of source electrode is calculated by Keldysh Green function method and multilevel Anderson model with d fold degeneracy. Boltzman equation is a very useful tool in classical transport properties of semiconductor. For quantum transport properties Kubo formula is adequate in linear response region. Nonequilibrium many body problem (present case) is very difficult , Keldysh formulation (Kadanoff-Baym formulation) is a recognized tool to solve it. The magnitude of tunneling current is determined by tunneling rate from QDs to electrodes, therefore we need to obtain a precise value of tunneling rate. Stabilization method will be used to evaluate the tunneling rate between the terminals and QDs. Phase shift method is not adequate to obtain the tunneling rate in the case of QDs, because the wave functions of the QDs are very difficult to get an analytic form. In order to design the single photon generator (SPG) operating at room temperature, optical properties of Ge QD array would be studied. Single InAs QD embedded in p-n junction has been demonstrated as a useful single photon generator, but it works at extremely low temperature. Existing III-V semiconductors have some difficulties in the implementation of SPG at room temperature. In the final year project we attempt to develop SPG by the experience of SETs at room temperature. Eventually, the detail layout of single Ge QD embedded in pn junction will be proposed. 研究期間:9308 ~ 9407
    Relation: 財團法人國家實驗研究院科技政策研究與資訊中心
    Appears in Collections:[電機工程學系] 研究計畫

    Files in This Item:

    File Description SizeFormat

    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明