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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/44673


    Title: 一個快速立體視覺系統的嵌入式硬體設計;Embedded Hardware Design of a Fast Stereo Vision System
    Authors: 陳伯瑞;Bo-ruei Chen
    Contributors: 資訊工程研究所
    Keywords: 立體視覺;嵌入式硬體設計;stereo vision;embedded hardware design
    Date: 2010-07-26
    Issue Date: 2010-12-09 13:52:23 (UTC+8)
    Publisher: 國立中央大學
    Abstract:   立體視覺廣泛運用於各種領域,在日常生活中亦發展出許多應用,例如:虛擬實境、自動導航機器人,自動追蹤與安全監控系統,和3D人機互動介面系統等等。由於立體視覺演算法複雜耗時,而且許多應用需要即時性的系統效能,因此需要設計一個滿足即時性的立體視覺硬體平台。   本研究提出一個適合硬體實作的即時立體視覺系統架構。並基於高階系統硬體設計方法論,以未校正影像經過影像前處理與連通物件標定找出感興趣區塊,例如面積較大的障礙物,接著以區域匹配方法中的區塊匹配 (SAD)進行立體匹配得到disparity,最後經由查詢事先量測好的 disparity-深度關係表格得到深度資訊。在硬體實作上,首先使用 IDEF0技術將系統進行階層模組化,再以Grafcet將經過高階語言驗證的演算法進行離散事件建模,接著將 Grafcet模型轉譯成VHDL硬體電路。我們設計並實作了影像前處理模組和立體匹配模組的嵌入式硬體,並設計管線化控制器將各個硬體模組整合為一個高速、平行架構的立體視覺系統,最後於 FPGA晶片進行硬體的驗證。   硬體實驗結果顯示:本系統在92.34 MHz的系統時脈下,可以達到每秒28張(28 FPS)立體影像深度估測的效能。對於低複雜度場景的立體視覺應用,可充分滿足即時性的效能需求與準確性。相較於傳統使用高性能CPU或GPU的立體視覺解決方案,本研究所實現的立體視覺系統具有精簡、低成本和高性能的優點。  Stereo vision has been widely used in many fields and our daily life, such as virtual reality, auto-navigation of mobile robot, auto-tracking and security monitoring system, and 3D human-machine interaction system, etc. Due to high computational complexity of stereo vision algorithm and needs of real-time system performance, it needs to design a real-time stereo vision hardware platform.   In this thesis, we propose a real-time stereo vision system architecture and it is suitable for hardware implementation. Based on high-level system hardware design methodology, our proposed method finds regions of interest (ROI), such as big obstacles, from un-calibrated stereo images by image preprocessing and connected component labeling, and then processes local stereo matching with block-based match metric, SAD, to get disparity, and finally gets depth information from a lookup disparity-depth relation table. About hardware implementation, we use IDEF0 to set up systematic stratum module at first, and then perform the discrete modeling of the software-proved algorithm with GRAFCET, and translate VHDL hardware circuit from GRAFCET models. We design and implement not only image preprocessing IPs and stereo matching IP, but also pipeline controller to integrate all IPs into a high-speed and parallel architecture stereo vision system, and finally we verify hardware system on FPGA devices.   The result shows our system performance can achieve 28 frames per second (FPS) stereo images depth estimation under 92.34MHz clock rate. It fully satisfies the needs of real-time performance and accuracy for stereo vision application in low-complexity scene. By comparison with traditional stereo vision solution using high-performance CPU or GPU, our stereo vision system has advantages of simple, low-cost, and high-performance.
    Appears in Collections:[資訊工程研究所] 博碩士論文

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