超低功率及超高速之銻化物異質接面場效電晶體元件的開發(I); Development for Ultra-Low Power, Ultra-High Speed Antimonide-Based HFETs(I)

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題名:	超低功率及超高速之銻化物異質接面場效電晶體元件的開發(I);Development for Ultra-Low Power, Ultra-High Speed Antimonide-Based HFETs(I)
作者:	林恆光;綦振瀛
貢獻者:	電機工程學系
關鍵詞:	砷化銦;高電子可動度電晶體;InAs;high-electron-mobility transistor;電子電機工程類
日期:	2008-07-01
上傳時間:	2010-12-28 15:53:21 (UTC+8)
出版者:	行政院國家科學委員會
摘要:	通訊市場中越來越高的操作頻率要求及不斷降低之IC 供應電壓的工業標準，能夠操作在低電壓並具有高速傳輸性能的電晶體已經吸引越來越多的注意。相較於傳統砷化鎵的高電子可動度電晶體(HEMT)，以砷化銦為通道層的HEMT，具有更優異的傳輸性能。已有文獻證明，在相同元件性能下，砷化銦比起砷化鎵HEMT，其消耗功率僅需十分之一，比起磷化銦HEMT，亦僅需三分之一。因此從低功率及高速度的市場應用角度來看，此材料系統設計的HEMT，具有相當高的競爭性。本計畫第一年的目標，首先必須在砷化鎵基板上，利用分子束磊晶技術發展出具高電子可動度的砷化銦二維電子氣結構，其進行方式如下：(1)由於極大之砷化鎵及砷化銦格子常數的差異，緩衝層結構必須最佳化，以減少缺陷對傳輸性能的影響。(2)評估長晶製程參數對傳輸性能的影響(3)砷化銦導通層界面結構對傳輸性能的影響。低溫及室溫的Hall 可動度量測、輔以組成及結構上的觀察，為主要特性化此二維電子氣結構傳輸性能的研究方式。為解決載子衝擊離化電洞造成元件輸出電導異常的增加，吾將提出不同於文獻中的新元件結構，而這部分亦有賴於磊晶成長上作一系統的研究。基於所發展出的元件結構材料，本計畫第二年的前半段將專注於元件製程的發展，工作的內容主要包括光罩的設計、低Ohmic 接觸電阻的發展、評估溼式及乾式蝕刻用於定義元件平台的製程、光學微影閘極的製作、介電層的發展及內連線的製作。發展出穩定的元件製程後，這年度的下半段將第一年所發展出的各種結構製作成元件，用以評估衝擊離化效應對其電性的影響。本計畫第三年將運用所發展出最佳衝擊離化特性的元件結構，製做超高頻元件，工作的重點主要在發展奈米級的電子束微影的閘極製程。0.25 微米的閘極元件為前期的目標，期望能在後期發展出小於0.1 微米的閘極製程，並證明元件的超高頻性能。此外，吾亦將特性化此元件的1/f 及高頻雜音、消耗功率、功率密度、電流驅動能力及耐電壓等，以作為未來系統應用上的目的。藉由本計劃的進行，可將此砷化銦族的材料系統應用於高電子可動度電晶體的潛力作一系統的評估。除了證明改善的元件直流電性外，超低消耗功率下展現的高頻性能將提供單石微波毫米積體電路新的應用方向。本計劃除了上述之目標外，將就一些關鍵的技術作深入的學術研究。 High frequency performance added by reduced power supply is demanding in communication market. Any devices with superior transport properties and low operation voltge therefore draw more attention. Compared to conventional GaAs HEMTs, the ones with InAs as channel yield much higher electrical properties. The devices are very competitive from low-power and high-speed application points of view. However, a drawback of large amount of impact-ionized holes due to small InAs bandgap along with type II band lineup at InAs/AlSb hetero-interface results in abnormal high output conductance. We thus have to carefully design device structure to minimize the negative effect. In the first year of the project, we will develop InAs-channel 2-DEG structures with high mobility metamorphically on GaAs substrates by MBE technique. Due to very large lattice mismatch (7%) between InAs and GaAs, optimization of buffer layer for minimizing the defect effect on active devices is our first topic. The second is to evaluate the effect of growth parameters on transport properties. Finally, how interface structure affects transport properties will be studied. Temperature-dependent Hall measurement assisted by XRD, SIMS, AFM, and RHEED techniques for characterizing material composition and structure will be chosen as the primary study approach. It is emphasized that we will develop new device structures which can effectively reduce the impact-ionized hole effect on the devices. Growth study needs to be done to realize the ideas. Based on the developed device materials, we will focus on development of device fabrication for the first half of second year. Mask design, low contact resistance, dry or wet etch for mesa, optical gate, passivation, and interconnects are relative works involved in the development. In second half of the year, we will fabricate all of the developed device materials into working devices and study the impact ionization effect on the device behaviors. In the third year of the project, focus will be on realization of extra-high speed devices. Key work is in specific the development of the e-beam gates. A 0.25μm gate is our first-stage goal and a gate with dimension smaller than 0.1μm is expected in the final. We can therefore demonstrate ultra-high speed devices using the developed gate process. In addition to high-frequency performance noise, power dissipation, power density, current driving capacity, and breakdown voltage will also be characterized. Realization of the device with extra high frequency and low operation voltage added by optimized DC electric behaviors will provide a new possible direction for MMIC application. 研究期間：9610 ~ 9707
關聯:	財團法人國家實驗研究院科技政策研究與資訊中心
顯示於類別:	[電機工程學系] 研究計畫

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