| 摘要: | 現今微電子構裝系統中，為容納更高密度的I/O（Input/Output）數目在高階IC晶片上，覆晶接點(flip-chip bumps)尺寸將大幅縮小至50 μm以下。如此，每個覆晶接點所承受的電流密度將會高達104 A/cm2或更高，進而造成電遷移效應誘發失效行為(electromigration-induced failure)，此失效行為將嚴重IC晶片內覆晶接點之可靠度。因此，在此博士論文中，於第三章，我們先利用一個基本的覆晶式銅/錫/銅銲點結構去探討會發生的電遷移誘發失效模式與原因。在第四章中，深入去探討陰極銅/錫銲點界面其電遷移誘發失效行為機制；我們計算出銅金屬墊層其在電遷移效應下的消耗活化能(QEM)和銅在錫母體中的有效碰撞係數(effective charge number, Z*Cu/Sn)；得到這些參數後，我們可以定量出電遷移誘發銅在錫的電遷移原子通量(JCu,EM)和銅原子溶解通量(JCu,diss.)。一旦，得到以上兩個電遷移誘發原子通量，可以建立一個動力學模型去定義出：(1)電遷移誘發銅原子溶解通量主要驅動力和(2)抑制錫在錫母體中電遷移原子通量的“合金效應”。將JCu,EM和JCu,diss.做相等可以取得固定電流密度下的臨界溫度值(Tcrit.)，再利用這些臨界溫度值去描繪出陰極銅/錫界面電遷移誘發失效圖。同時也發現陰極界面上錫銅化合物的成長和電流密度與測試溫度有極大的關係。最後在第五章，根據先前學者的基礎模型，我們建構出更可靠與正確的陰極界面電遷移失效行為圖(銅墊層消耗，錫孔洞形成，陰極界面錫銅化合物成長)。 Abstract Due to the number of the I/O (input/outout) counts in the advanced IC will continue to increase quickly; the diameter of flip-chip bumps will approach to 50 μm and below. The current density in each flip-chip bumps could reach 104 Amp/cm2 or higher. While the high density of current flowing through the flip-chip solder bumps, EM (electromigration)-induced failure has become a serious reliability issues for the solder joint. Hence, in this work, we will first discuss what kinds of EM-induced failures would occur in a flip-chip Cu/Sn/Cu solder joint under EM test in Chapter 3. In Chapter 4, the entire EM-induced failure modes at the cathode Cu/Sn solder joint interface would be discussed in a great detail. In Chapter 4, we also calculated the activation energy for the Cu-pad consumption under the EM effect (QEM), and the effective charge number (Z* value of Cu in Sn (Z*Cu/Sn)). By knowing the activation energy for the Cu-pad consumption and the effective charge number, we can quantify both Cu EM flux in Sn solder matrix (JCu,EM) and EM-induced Cu pad dissolution flux (JCu,diss.). Once the above two EM-induced fluxes are deduced, a kinetic model is build to define: (1) the main driving force of the EM-induced Cu-pad dissolution and (2) “alloy effect” retarding the Sn EM flux in the Sn solder matrix. By equaling the JCu,EM and the JCu,diss., we can obtain the a critical temperature (Tcrit.) at a constant current density. Then, we can use various critical temperatures to plot a EM-induced failure map at the cathode Cu/Sn interface under EM effect. Also, the growth of interfacial Cu-Sn compounds at the cathode interface has been found to have a strong relationship with current densities and EM-test temperatures. Finally, based on previous researcher’s model, we can construct a more reliable and accurate plot of the EM failure behavior at the cathode Cu/Sn interface (Cu-pad consumption, Sn-voids formation, cathode IMCs formation) under EM effect in Chapter 5. |
