| 摘要: | 近年來在矽基半導體基材上製備規則有序奈米結構之研究逐漸受到廣泛的注意，主要是由於規則序化排列的奈米粒子及奈米線陣列已被發現在許多領域，如奈米電子元件、觸媒，高密度資料儲存媒體及生物感測器上，有很大的應用潛力。雖然有許多合成技術已被用以大量製備奈米粒子及奈米線材料，但要如何精準控制所製備奈米材料之尺寸、長度、生成位置、結晶指向等卻仍是目前相關研究急需克服的重大挑戰。在實際奈米元件應用上，能否精準控制奈米材料在有預置圖案定義之晶片特定地點上的成長方向、成長尺寸、成長位置，常是決定這些奈米材料能否真正整合至元件製程中最關鍵的部分。因此設計並研發能控制在矽基半導體晶片特定位置上製備有序排列之奈米材料陣列，無論在學術研究上或實際應用上皆是十分重要的。此外，當元件尺寸持續縮小至奈米尺度時，深入探究不同奈米尺度金屬材料與各式矽基晶片間經不同熱處理作用後其界面反應之變化及其對應的特性表現，其結果對釐清此反應生成之金屬矽化物能否真正應用於先進奈米元件中，將扮演一關鍵角色。因此，本計畫擬以三年為期，除需逐步添購實驗必須之設備外，在相關實驗執行規劃上將由能於矽基晶片上製備一系列新穎自組裝奈米模板製程技術著手，再針對以下九個子題分年分階段進行深入研究： (一) 表面電漿改質結合液面自組裝技術製備大面積規則奈米模板之製程設計與開發。 (二) 在有預置圖案(prepatterned)定義之晶片特定位置製備規則奈米球模板陣列。 (三) 奈米模板輔助製備0 維金屬及矽基半導體奈米點結構陣列之研究。 (四) 整合奈米模板與低溫濕式蝕刻製程以製備規則準直排列之Si，SiGe，及高摻雜 (heavily-doped) Si 奈米線結構陣列。 (五) 探究不同矽基基材之Si-Ge 成份比例、摻雜元素、不同反應區域尺寸對製備奈米線之影響及其生成反應動力學。 (六) 先進矽基(SiGe, SOI, heavily-doped Si)晶片上控制生成低電阻矽化物奈米點陣列之製程研發及其界面反應機制研究。 (七) 奈米模板結合電化學鍍膜技術製備尺度可調變、準直排列之新穎金屬及金屬/半導體異質奈米結構陣列。 (八) 新穎3D 垂直式金屬矽化物奈米結構陣列之設計與製備。 (九) 掌握在各式矽基晶片上製備低維度、優質新穎奈米結構陣列之最佳製程參數及其特性研究。 Recently, the fabrication of periodic nanostructures on Si-based substrates has been of considerable interest, because well-ordered nanoparticle and/or nanowire arrays have already been found their potential applications in many areas such as nanoelectronics, catalysts, high-density data storage media, and biosensors. A variety of synthesis techniques have been developed to synthesize large-scale nanoparticles and nanowires. However, the precise controls of size, length, location, and crystallographic orientation of the nanomaterials produced are still the major challenges. Since accurate controls of the growth orientations, sizes, and locations of nanomaterials on Si-based substrates with designed patterns are essential for the practical applications of the nanomaterials in nanodevices, it is of scientific and practical significance to fabricate periodic nanomaterial arrays at specific positions on the patterned Si-based substrates. On the other hand, as the dimensions of device structures continue to shrink to nanometer regime, in-depth understanding the interactions of nanoscale metal contacts with Si-based substrates after different heat treatments will play an important role in defining the application of metal silicide contact in advanced nanodevices. The objectives for the three-year project are to develop novel technologies for self-assembly of nano-templates on Si-based substrates to allow the nanostructures to be formed controllably and nanodevices to be fabricated. The main tasks include： 1. Fabrication of large-area well-ordered nano-templates by surface plasma treatment process in conjunction with liquid surface self-assembly technique. 2. Fabrication of periodic nanosphere templates on prepatterned Si-based substrates. 3. Nanotemplate-assisted fabrication of 0-D metal and Si-based semiconductor nanodot arrays. 4. Fabrication of periodic arrays of vertical Si, SiGe, and heavily-doped Si nanowires by using the nanotemplate lithography technique in conjunction with the selective chemical etching process. 5. Effects of composition, dopants, and reaction-area size on the formation kinetics of Si-based nanowires. 6. Fabrication of low-resistivity silicide nanodot arrays on the advanced Si-based substrates. 7. Fabrication of size-tunable, vertically-aligned periodic metal and metal/semiconductor heterogeneous nanostructure arrays by using the nanotemplate lithography in conjunction with the electroplating technique. 8. Design and fabrication of novel 3D vertical metal silicide nanostructure arrays. 9. To establish the optimum process conditions for fabrication of low-dimension, high-quality nanostructure arrays and their properties characterization. 研究期間：9908 ~ 10007 |
