本研究計畫的主要目的，是發展全新之導波模態共振-表面電漿子(GMR-SPP)波導技術，經由模態理論分析與實體製程開發，將極具潛力的表面電漿子波導引入晶片間或晶片內部光學連結之實際應用。平面式表面電漿子波導已經成功被運用於晶片對晶片之光學連結，然而該技術瓶頸在於不同元件間與表面電漿子波導的模態差異過大，進而產生嚴重的耦合損耗。此外，目前的表面電漿子波導尚難與光電晶片單石化整合，在構裝上的高對位精度要求與成本考量，尚難實際推廣與應用。本計畫將結合導波模態共振與表面電漿子結構，提出與SOI 波導模態尺寸相近的GMR-SPP 波導，解決表面電漿子波導耦光效率過低的問題，並可藉半導體製程，使SOI 波導與GMR-SPP 波導可單石積體化於SOI 基板上。本三年型之研究計畫內容將包含有：一、導波模態-表面電漿子之雙重共振模態耦合理論探討與GMR-SPP 波導之製程開發；二、GMR-SPP 波導與SOI 波導之高效率模態耦合設計與單石積體化結構整合製程開發；三、GMR-SPP 波導與面射型雷射之異質化耦光結構設計與覆晶封裝技術開發。此外，導波模態共振與表面電漿子結構之色散關係、角頻譜分析等也將會被探討。藉由本計畫所提之GMR-SPP 波導技術將可以實現於SOI 基板上，除了可以單石積體化整合光路外，SOI 基板還相容於電子IC 元件之CMOS 製程，因此可以期待一兼具高速光連結與多工之SOC 晶片的實體化應用實現。 This research focuses on developing the new waveguide technology combined with guide-mode resonance (GMR) and surface plasmon polariton (SPP) effects. Based on the mode coupling analysis and fabrication process development, the recently potential SPP waveguides would be introduced into inter-chip or intra-chip optical interconnect applications. Planar SPP waveguides have been already successfully applied into chip-to-chip optical interconnects; however, the bottleneck of this technique is the strong mode-mismatches between various components and SPP waveguides, resulting in serious coupling losses. Moreover, it is still difficult to monolithically integrate the optoelectronic chips and SPP waveguides. Restricted by the very tight alignment tolerance and cost considerations, the SPP-waveguide-based optical interconnects are still hard to optical interconnect application in practice. Based on an integrated structure with dual GMR and SPP effects, a novel GMR-SPP waveguide with a relatively large mode size compatible to SOI waveguide is proposed in this research, which could address the low coupling efficiency between SPP waveguides and other components. In addition, by using the semiconductor lithography processes, this GMR-SPP waveguides could be monolithically integrated into the SOI-based planar lightwave circuits. The objectives of this 3-year research proposal are composed of: (i) the theoretical investigation to the mode coupling of dual GMR-SPP resonance effects and its fabrication process development; (ii) the mode-matching design between the GMR-SPP waveguide and SOI waveguide, and its monolithically-integrated process development; (iii) the optical coupler design between GMR-SPP waveguide and vertical-cavity surface-emitting laser (VCSEL), its fabrication process, and the flip-chip packaging developments. In addition, the dispersion relations and angular spectrum analyses would be also addressed in this research. Based on this proposed GMR-SPP waveguides realized on the SOI substrates, this optoelectronic chip could not only monolithically integrate the lightwave circuits, but also be compatible to the CMOS processes for electric ICs; therefore, a high-speed optical interconnect and intelligent system-on-chip (SOC) functionalities could be realized within a single chip. 研究期間：9908 ~ 10007
