多核心晶片（Multi-core chip）已成為目前晶片設計之新趨勢與解決方案，許多先進之晶片皆已採用多核心架構。但複雜度遠高於單核心晶片之多核心晶片為測試帶來許多挑戰與難題，尤其多核心晶片內使用多階層與大量之記憶體，多核心晶片的良率與可靠度將被這些記憶體所支配。多核心晶片內記憶體因採取多階層式與網路晶片（network-on-chip）架構，可分為同質性（homogeneous）記憶體與連接於網路上之異質性（heterogeneous）記憶體。本計畫將針對多核心晶片內同質性與異質性記憶體發展測試、診斷及修復相關技術，提高晶片之良率與可靠度。第一年，我們將分別研究適用於多核心晶片內同質性與異質性記憶體之測試方法，開發低面積技術來實現此測試方法，並提供增加可靠度的透明測試方法。第二年，我們將分別設計同質性與異質性記憶體之診斷技術，包含可降低診斷資料之壓縮技術與具瑕疵定位能力之透明自我診斷技術。第三年，我們將分別開發用於同質性與異質性記憶體之自我修復技術，以及具有線上特性之高可靠度自我修復系統。 Multi-core architecture has been a trend and solution for designing complex system chips. However, the complexity of multi-core chips is much higher than that of single-core chips, such that it brings many challenges on testing. Especially, the yield and reliability of multi-core chips are dominated by those of memory cores. Memory cores in multi-core chips can be classified into two categories: homogeneous memory cores and heterogeneous memory cores. This project will develop testing, diagnosis, and repair techniques for homogeneous and heterogeneous memories to enhance the yield. Also, the transparent test, diagnosis, and repair techniques will be developed to improve the reliability of memories. In the first year, we will develop low-area BIST schemes for homogeneous memories and heterogeneous memories. Also, low test-complexity transparent test scheme will also be developed to enhance the memory reliability. In the second year, we will develop efficient built-in self-diagnosis schemes with diagnostic data compression capability for homogeneous memories and heterogeneous memories. In the third year, we will develop efficient built-in self-repair schemes for homogeneous memories and heterogeneous memories with complex redundancy structures. We will also develop transparent built-in self-repair scheme for memories. 研究期間：9908 ~ 10007
