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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/48399


    Title: 嵌入式立體視覺系統設計與硬體實作;System Design and Hardware Implementation of Embedded Stereo Vision
    Authors: 吳少龍;Shau-lung Wu
    Contributors: 資訊工程研究所
    Keywords: 嵌入式系統;立體視覺;SAD;Stereo vision;embedded system;k-means
    Date: 2011-07-18
    Issue Date: 2012-01-05 14:53:30 (UTC+8)
    Abstract: 典型的立體視覺原理係基於雙攝影機同步取像和一系列複雜的影像處理計算,因此通常需要高速的處理器才足以因應複雜演算法的實作。低成本、計算資源受限的嵌入式系統應用,例如機器人視覺或人機互動介面系統,立體視覺則難以實現。本研究將設計了一個高性能的嵌入式立體視覺系統,我們設計了高速雙攝影機取像控制器,並且將立體視覺的演算法實現為管線化硬體電路,以滿足即時嵌入式系統應用目標。我們先以K-means演算法對影像進行色彩分群,再將影像物件分割後,透過連通物件標定得到物件資訊,接著以SAD(Sum of Absolute Difference)方法計算每個物體在左右影像的視差(disparity),最後藉由查表得到深度資訊。所有的演算法均已實作為硬體,並藉由上層的管線控制器整合為一顆平行化的立體視覺晶片。並為了驗證立體視覺晶片系統的性能,我們在FPGA實驗平台上整合了兩個取像速度為60 frames/sec,VGA解析度的攝影機,我們的立體視覺晶片在低複雜度場景下,可達每秒鐘15張立體視覺深度影像輸出的效能,此一優異的性能足以使本系統應用在各種即時嵌入式系統。 A typical stereo vision principle is basically consisted of two parts. One is the imaging extracted using two synchronous cameras and followed by a series of complex image processing calculations. However, high-speed image processors are often required to implement complex algorithms. Thus, stereo vision is very difficult to be achieved on the embedded computing system applications, such as robot vision or human-machine interactive interface system, because of its low-cost and constrained resources. In this paper, we designed a high-performance embedded stereo vision system. To meet the goal of real-time embedded system, a high-speed dual-camera controller was created and the stereo vision algorithms were implemented as pipelined hardware circuitry. We first used K-means algorithm to group colors. Then, we obtained the information of separated objects by calculating connected components. Furthermore, for each objects, the SAD (Sum of Absolute Difference) method was applied to calculate the disparity between the objects in the left and right image. Finally, we get the depth of each object by looking up the disparity-depth lookup table. All the algorithms were implemented as hardware systems and integrated into a stereo vision chip with a pipeline controller in the top layer. In order to verify the performance of stereo vision chip system, we integrated two cameras with high speed (60 frames / sec) and VGA dpi on the FPGA platform. As a result, our stereo vision chip is able to generate images at the speed up to 15 images / sec under a low-complexity background. This outstanding performance makes our system easily be used in a variety of real-time embedded systems.
    Appears in Collections:[資訊工程研究所] 博碩士論文

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