| 摘要: | 現代通訊系統中，低相位雜訊的壓控振盪器是不可或缺的元件，由於高資料傳輸量的需求，促使我們研究高頻的通訊系統。因此，如何設計高頻率並同時具有低相位雜訊的振盪器是一個值得探討的重點。另外，四相位的振盪器也常被用在直接轉換的收發機系統中，本論文中也針對如何直接量測四相位壓控振盪器之振幅及相位誤差作了探討。 本論文的主題在於使用互補式金氧半場效電晶體及鉮化鎵異質接面假晶格高電子移動率電晶體製程，設計並實現微波及毫米波振盪器，研究的方向著重在應用於K頻段的低功耗、低相位雜訊差動及四相位壓控振盪器。論文主要可分為四大部分，第一部份介紹振盪器之設計參數、理論及應用於共振腔中的被動元件之設計。第二部分提出了新型具有低功耗及低相位雜訊的差動振盪器。第三部分則探討使用鉮化鎵異質接面假晶格高電子移動率電晶體製程來設計考畢茲振盪器之優缺點。論文的最後一部分主要在介紹四相位振盪器的原理、應用及架構，並且提出新型的四相位振盪器，同時說明其設計概念及直接量測相位、振幅誤差的方法。 首先我們使用台積電90奈米CMOS製程實現了K頻段使用變壓器回授及電流再利用架構之壓控振盪器。量測結果顯示，此電路振盪頻率可調範圍為21.3 ~ 20.3 GHz，並且在1-MHz偏移時的相位雜訊為-116.4 dBc/Hz，功率消耗為3毫瓦，輸出功率為-16 dBm，並且僅佔用0.36 mm2的晶片面積，優位指數(FOM)為-198 dBc/Hz。此晶片也可經由雷射切割來修改其振盪頻率，切割後的電路振盪頻率為25.1 ~ 23.6 GHz，並且在1-MHz位移時的相位雜訊為-120 dBc/Hz，功率消耗為6.9毫瓦，輸出功率為-12 dBm，優位指數(FOM)為-199.4 dBc/Hz。 接下來是使用穩懋鉮化鎵異質接面假晶格高電子移動率電晶體製程所設計的考畢茲壓控振盪器。總共討論了三種使用不同回授的電路架構，包含使用變壓器回授、不使用變壓器回授、同時使用變壓器回授及閘極電感回授等。量測結果說明變壓器回授應用在考畢茲振盪器上會造成反效果，所以建議在設計時使用閘極電感回授即可。三個電路的晶片面積皆為1 mm2，與CMOS製程比較起來，使用此製程之振盪器具有較高的輸出功率及效率。 最後一部分為使用台積電90奈米CMOS製程來實現的新型K頻段四相位壓控振盪器，此電路採用融合了第一部分差動振盪器的優點並且採用串聯耦合形式，所以能達到非常低的功耗。量測結果顯示，此電路振盪頻率可調範圍為20.6 ~ 21.2 GHz，並且在1-MHz偏移時的相位雜訊為-117.2 dBc/Hz，功率消耗為6.3毫瓦，輸出功率為-15 dBm，相位及振幅誤差分別為4度及0.6 dB，優位指數(FOM)為-195.6 dBc/Hz，並且僅佔用0.77 mm2的晶片面積。 In modern communication systems, voltage-controlled oscillator (VCO) is an in-dispensable building block. Since the demand for high data transmission rate is increas-ing, we were driven to investigate high-frequency communication systems. Therefore, how to design a high-frequency and low phase noise VCO is an important issue to be explored. In addition, since a quadrature VCO (QVCO) is commonly used in the di-rect-conversion transceivers we also discussed the measurement method of phase and amplitude error. Our researches were focused on using CMOS and GaAs PHEMT processes to de-sign and realize microwave and millimeter-wave VCOs and the circuit design was fo-cused on K-band low power and low phase noise differential and quadrature VCOs. There are four parts in the thesis. In the first part, the design parameters, oscillator the-ory, and the design of passive components in an LC-tank were introduced. In the second part, we proposed an innovative low power low phase noise differential VCO. In the third part, the pros and cons of using GaAs PHEMT process to design the Colpitts VCOs were investigated. In the last part, operation principles, application and topologies of QVCOs were introduced, an innovative QVCO was proposed, and the measurement method of phase and amplitude error was explained as well. Firstly, we used TSMC 90 nm CMOS process to realize a K-band VCO with transformer-feedback and current-reused techniques. The measured results showed that the oscillation frequency can be tuned from 21.3 to 30.3 GHz. The phase noise is -116.4 dBc/Hz at 1-MHz offset. The dc power consumption is 3 mW and the output power is -16 dBm. The chip size is only 0.36 mm2. The VCO demonstrated a Figure of Merit (FOM) of -198 dBc/Hz. This chip can also be laser-cut to modify its oscillation fre-quency. After being laser-cut, the oscillation frequency can be tuned from 25.1 to 23.6 GHz. The phase noise is -120 dBc/Hz at 1-MHz offset. The dc power consumption is 6.9 mW and the output power is -12 dBm. The laser-cut VCO demonstrated a FOM of -199.4 dBc/Hz. Secondly, we used WIN GaAs PHEMT process to design Colpitts VCOs including three circuits with different feedback topologies. These are the modified VCOs with transformer feedback, without transformer feedback, and with transformer and gate in-ductive feedback. The measured results showed that applying transformer-feedback technique to the Colpitts oscillator will cause counter effect. Therefore, the Colpitts os-cillator with gate inductive feedback only was recommended if large bandwidth is pre-ferred. Each of three chips occupies a chip size of 1 mm2. Compared to the CMOS pro-cess, the VCO using this process has larger output power and efficiency. Finally, we used TSMC 90 nm CMOS process to realize an innovative K-band QVCO. This circuit was based on the differential version of previously proposed CMOS VCO and adopted the bottom-series coupling topology. Therefore, ultra-low power consumption was achieved. The measured results showed that the oscillation frequency can be tuned from 20.6 to 21.2 GHz. The phase noise is -117.2 dBc/Hz at 1-MHz offset. The dc power consumption is 6.3 mW and the output power is -15 dBm. The minimum I/Q phase and amplitude error are 4° and 0.6 dB, respectively. The QVCO demonstrated a FOM of -195.6 dBc/Hz. The chip size is only 0.77 mm2. |
