矽半導體產業自發展至今40 餘年來始終遵循著莫爾定律，但隨著半導體元件尺寸微縮進入奈米世代，導入新材料或新結構以增進元件運作效能便成為十分重要的課題。矽鍺碳半導體合金材料與其形變技術因為可以提供高載子移動率且可使目前微電子及光電元件更具功能性而受到廣泛且深入的研究。本研究計畫提出整合矽鍺碳磊晶薄膜技術與氧化多孔矽誘發形變技術以製作超高形變矽基板與矽鍺虛擬基板，預期能製作出拉伸形變量大於2.5%之形變矽基板、鍺濃度高於50%之矽鍺虛擬基板及具拉伸矽/壓縮矽鍺雙形變複合基板；本計畫亦研究各種形變基板圖案化至奈米尺度後之應變行為模型，並建立顯微拉曼散射光譜解析奈米尺度應變之技術；本計畫同時開發適用於高形變或高鍺濃度基板的新型金屬矽鍺化物材料，研究其生成行為對於奈米尺度形變結構之影響，並製作形變矽奈米線金氧半場效電晶體以驗證此製程技術之整合性。而本計畫亦選用適當功函數的金屬矽鍺化物搭配奈米尺度形變結構開發製作蕭基能障二極體，分析其元件特性。由於本研究計畫與現今矽製程技術高度相容，因此相關的研究成果將成為未來製作高載子遷移率元件以及總計劃整合先進元件增強技術的重要參考。 For more than 40 years, the integrated circuit industry has followed a steady path of constantly shrinking device geometries and increasing chip size, commonly referred to as “Moore’s Law.” However, continued downscaling of CMOS transistors faces immense challenges as device miniaturization does not necessarily yield performance enhancement. Novel materials or device structures are therefore being actively explored to improve the transistor performance. Recently, Si1-x-yGexCy semiconductor alloys and strain engineering have attracted intensive research interest because they offer enhanced carrier mobilities and more functionalities for the state-of-the-art electronics and optoelectronics. In this project, we propose to fabricate a variety of strained substrates with the use of oxidized porous Si as stressor. We expect to create (1) highly strained-Si substrates with tensile strain larger than 2.5%, (2) SiGe virtual substrates with Ge concentration more than 50%, and (3) tensile-strained-Si/compressive-strained-SiGe composite substrates. We also develop the Micro-Raman measurement technology to effectively characterize and analyze the patterning-induced asymmetric relaxation in nanoscale patterned substrates. New metal silicides/germanides are also explored in this project for integration with highly strained or high-Ge-concentration substrates. The influences of metal silicidation, such as Ge segregation and thermal stress, on nanoscale patterned heterostructures would be systematically investigated. To verify the feasibility and integration of the developed materials, we also develop the fabrication process and study the performance of strained-Si nanowire FETs. Finally, we develop silicide/germanide Schottky barrier diodes based on nanoscale patterned heterostructures and their Schottky barrier heights will be characterized. These results will provide useful information for fabricating high-mobility devices and integrating main-project enhancement technologies developed for advanced CMOS. 研究期間：10008 ~ 10107
