旋積盲訊號源分離結合後處理之演算法及超大型積體電路架構設計;A Study of Algorithm and Vlsi Architecture Design for Convolutive Blind Source Separation with Post-Processing (Ii) (Iii)

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Title:	旋積盲訊號源分離結合後處理之演算法及超大型積體電路架構設計;A Study of Algorithm and Vlsi Architecture Design for Convolutive Blind Source Separation with Post-Processing (Ii) (Iii)
Authors:	王家慶
Contributors:	資訊工程系
Keywords:	Convolutive Blind Source Separating;Speech Enhancement;Direction of Arrival Estimation;VLSI;Silicon Intellectual Property;研究領域：電子電機工程類
Date:	2011-08-01
Issue Date:	2012-01-17 19:05:20 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	本計畫主要在研究旋積盲訊號源分離結合後處理之演算法以及其超大型積體電路架構設計。前期一年計畫“旋積盲訊號源分離結合後處理之演算法及超大型積體電路架構設計 NSC98-2218-E-008-012 ” 計畫 (執行期限2009/12/01~2010/10/31)，目的在發展演算法，本期兩年計畫將延續成果，進行演算法之VLSI架構設計。本計畫首先提出一有效之旋積盲訊號源分離方法，之後並將進一步提出兩種型式的旋積盲訊號源分離結合後處理之演算法及其應用: 分別是語音增強以及音源方位估測。本期兩年計畫將發展旋積盲訊號源分離結合後處理之演算法中關鍵模組之單晶片矽智產，並配合一般用途處理器完成晶片系統實現。為了能達成可攜式的應用，低功率的設計亦是本計畫的重點，我們將發展的三個矽智產說明如下: 旋積盲訊號源分離矽智產: 此矽智產將處理旋積盲訊號源分離演算法中之關鍵運算。旋積盲訊號源分離演算法中，線性預測前處理、分離矩陣求取、頻域排列問題的解決等模組皆牽連大量且複雜之演算，本計畫將設計其專有之矽智產架構。語音增強矽智產: 此矽智產將處理語音增強(第一種型式的後處理及其應用)中之關鍵運算。語音增強演算法中，子空間拆解的運算量龐大，我們將運用子空間追縱大幅減少運算量，並設計其專有之矽智產架構。音源方位估測矽智產: 此矽智產將處理語音增強(第二種型式的後處理及其應用)中之關鍵運算。本計畫利用解決頻域的排列問題的方向樣形分析方法來進行音源方位估測，在此方法中，適應性串接式分離器與類神經網路皆牽連大量且複雜運算，本計畫將設計其專有之矽智產架構。本期計畫全程共計二年，第一年預定達成目標包括下列五項： 1. 完成軟體與硬體的切割 (hardware/software partition)。 2. 完成旋積盲訊號源分離之矽智產架構設計。 3. 完成子空間語音增強後處理之矽智產架構設計。 4. 完成音源方位估計後處理之矽智產架構設計。 This project proposes a study on algorithm and VLSI architecture design for convolutive blind source separation (CBSS) with post-processing. The previous-term project NSC98-2218-E-008-012 focuses on the algorithm development. In this new-term project, we will work on the corresponding VLSI design. In the previous-term project, an effective approach to perform convolutive blind source separation is proposed and two types of its post-processing, speech enhancement and direction of arrival estimation, are proposed. This new-term project will present silicon IP designs for the key computations in convolutive blind source separation with post-processing. We will also integrate a general purpose processor with the proposed silicon IP modules to realize the whole VLSI system. Besides, a low power design is essential to enable the proposed system to be used in portable applications. The three silicon IP modules are illustrated as follows. CBSS IP: This IP performs the key computations in the convolutive blind source separation algorithm. In this algorithm, LPC prediction filter, separating matrix determination, and permutation problem solving are highly complex. Therefore, this project will propose its dedicated silicon IP design. Speech enhancement IP: This IP performs the key computations in the first type post-processing, speech enhancement. The subspace speech enhancement is used to eliminate background noise. Since the computational load of eigen-decomposition is heavy, this project will propose its dedicated silicon IP design. DOA IP: This IP performs the key computations in the second type post-processing, estimation of direction of arrival (DOA). This project uses directivity pattern analysis to solve the permutation problem in CBSS. The directivity pattern analysis method will be improved to enable the direction of arrival to be accurately estimated. The computational load of the cascaded separator and the neural network are heavy. Therefore, this project will propose its dedicated silicon IP design. This proposal will be completed in two years respectively. The main items in the first year are shown as follows: 1. Complete the hardware/software partition. 2. Complete the silicon IP design for convolutive blind source separation. 3. Complete the silicon IP design for subspace-based speech enhancement. 4. Complete the silicon IP design for direction of arrival estimation. 5. Complete testable design and low power design. The main items of this proposal in the second year are shown as follows: 1. Use FPGA platform to verify the proposed silicon IP modules. 2. Complete the VLSI architecture design which integrates a general purpose processor and the above three silicon IP modules. 3. Use CAD tools to fulfill the physical design of the proposed chip and authorize CIC to manufacture. 4. After receiving the chip, verify and test the functions and find out reasons for any errors. If necessary, fabricate an integrated chip for the second time. 5. Complete the whole system implementation and verification. 研究期間：10008 ~ 10107
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Computer Science and information Engineering] Research Project

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