| 摘要: | 本計畫『良率導向之類比陣列區塊電路自動產生器(II)』為『良率導向之類比陣列區塊電路自動產生器(I)』的延續計畫。在本年度計畫中，提出運用元件間存在的相關特性，在元件實體佈局中，因空間位置不同及製程變動，所造成的匹配或不匹配現象，擬以統計量線性相關系數來做為此匹配或不匹配的數學模型，尤其是針對類比陣列區塊電路，有別於現有的對稱匹配法則，利用同質且等向隨機的空間相關性，能為實體層設計時，建構一新穎的評量，進而提出元件擺置方法，此種能利用製程設計套件，並在數分鐘產生的先進虛擬擺置，因為原本要等待數天或數星期直到佈局工程師完成佈局後才可進行分析評估，現在可以提供在設計早先階段能預估其相對應的電路良率，這對一個非佈局專長的電路設計者而言，這是一個很新穎的構想，也是非常有助益的；據此，再配合類比陣列區塊電路自動佈局擺置和繞線平台的開發，產生完整的區塊佈局，以達到混合訊號積體電路設計快速、高精確度、高良率的需求，同時亦可依製程設計套件要件，經製程驗證後，建構為新資料庫單元細胞，可利重複始用以及系統整合。因此，可以大幅降低設計上的修改成本，並加速產品上市時間。在本年計畫中，分 3 個進程: 結合製程變異之邏輯佈局、考量實體佈局與繞線、以及整合邏輯佈局與實體補償之良率導向電容陣列區塊電路自動產生器，擬針對電容陣列，希望能開發一考量隨機與系統性不匹配，使用相依變動警覺模擬的電容陣列區塊電路自動佈局平台，以適應奈米時代單晶片系統量產可行性設計。吾人欲以Matlab 為發展平台，整合各個目前設計流程中的模擬設計工具，例如線路模擬器HSpice，佈局軟體 Laker，電阻電容參數萃取軟體Calibre 等。以常見的開關電容架構式之類比電路為實例，實際測試所開發的分析設計平台。 This project “Yield-aware Automatic Generator for Analog Regular Array Blocks((II)” is a continuous project of “Yield-aware Automatic Generator for Analog Regular Array Blocks((I).” In this sub-project, it aims to address the impact of device correlation on the yield enhancement of mixed-signal/analog integrated circuits. The statistical correlation of device parameters depends on spatial locations. Thus, the relationship between correlation and variation of device matching or mismatching can be modeled according to their relative placements. For analog regular array blocks, traditionally, the layout placement of a matching pair of devices is performed by the principle of comment centroid. It is to propose a novel design methodology for device allocation in early design stage by using the capability of homogeneous isotropic random (HIR) spatial correlation. The advanced virtual placement (AVP) is a physical-level placement that can be generated, based on process design kit (PDK), early in the design cycle, in minutes, by circuit designers who are not layout experts. Today, an engineer who wishes to study the physical effects of an analog design must wait until the layout designer has finished the layout, which could take days or weeks. To move to more advanced process nodes, it will be more important than ever to have an accurate analog layout early in the design cycle. It is to explore how the circuit performance is affected by the spatial correlation in advanced technology and to improve the design yield. Accordingly, an automatic variation/yield-aware analog-array-block place-and-route platform is developed in order to accommodate to the need of design for manufacturability in a nanometer technology era. The generated block layout is also put into the P-cells in PDK as for re-use and system integration later. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed-up the time to market for high-speed, high-precision, and high yield of mixed-signal IC design. In this project, it contents 3 topics, including logic-ratio assignment by considering process variation, physical assignment and routing for physical-ratio, balanced assignment and routing by compensation. It is to achieve the reliability and quality of products in nanometer semiconductor technology, this project will provide the automatic layout platform that considers the random and systematic mismatches of the devices. Our system platform will be developed in Matlab by integrated with the simulation and design tools, like HSpice and Laker, in current design flow. The common circuits of Switched-Capacitor analog circuits are used to verify the developed platform. 研究期間：10008 ~ 10107 |
