在此三年計畫中將以3D 方式用直通矽晶穿孔(Through-Silicon Via, TSV)技術進行資料與資料的收發動作，在第一年將分析TSV 的寄生負載效應並建立通道模型，並與子計畫二合作，研究包含TSV 通道模型與電源輸送之相關電路設計技術。並針對高速串列傳輸技術研發串列轉換器與展頻時脈產生器做研究與探討。在3D IC 測試技術方面與子計畫四合作，共同制定3D IC 測試技術與介面電路之間相關測試訊號傳輸規格。第二年則以第一年的TSV 模型為基礎，根據頻率衰減來設計等化器，確保經TSV 模型衰減的資料被補償回來，且在第二年與子計畫二、三合作，開發應用於TSV 通道模型的電源輸送架構之模擬平台與自動化技術。在高速串列傳輸部分設計時脈資料回復電路，使得失真訊號得以回復其原始訊號與時脈並且同時設計穩壓電路提供穩定的電源。另外在測試介面類比前端電路與子計畫四合作，研發應用於3D DRAM 測試技術之相關介面電路設計。第三年部分將與子計畫二、三合作，完成包含TSV 通道模型的系統模擬平台與電源輸送自動化擺置技術。在子計畫一的第三年整合第一及第二年電路設計，最終完成應用於TSV 通道傳輸與有線傳輸之高速傳送收發器，並且做晶片下線及在電路版上驗證此高速傳送接收器，同時與子計畫四合作，在第三年整合可測性技術完成3D DRAM 自我測試實體層設計。 In the three years project, the data transmission will use 3D-TSV technology to transmit data. In the first year, the TSV’s parasitical loading effect and channel model will be analyzed. The TSV’s channel model and power transmission circuit will be designed and analyzed together with sub-project 2. The high-speed serial links and spread-spectrum clock generator will be researched and discussed. To work together with sub-project 4, the 3D IC testing technology and interface circuit’s testing signal will be established. In the second year, the equalizer will be designed base on the first year’s TSV channel model. Therefore, the TSV’s channel loss will be compensated. To work together with sub-project 2 and 3, the simulation platform and automatic technology of TSV channel model’s power transmission architecture will be developed. The clock and data recovery will be designed in the high-speed serial link. Therefore, the distorted signal can be recovered. The power regulated circuit will be designed to provide regulated power. The analog front-end testing interface circuit will work together with sub-project 4 to develop the 3D DRAM testing interface circuit. To work together with sub-project 2 and 3 in the third year, the system simulation platform and power automatic place technology of TSV channel model will be completed. Finally, the first and the second year’s circuit will be integrated to a high-speed serial-link transceiver for TSV application. The high-speed transceiver will be tape-out and verified in the PCB. To work with sub-project 4, the physical layer of 3D DRAM self-test technology will be integrated. 研究期間：10008 ~ 10107
