應用於三維積體電路之設計、自動化與測試關鍵技術-子計畫四：應用於三維積體電路之可測性設計技術與自動化(I);Design-For-Testability Techniques and Automation for 3d Ics

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/49655

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/49655

Title:	應用於三維積體電路之設計、自動化與測試關鍵技術-子計畫四：應用於三維積體電路之可測性設計技術與自動化(I);Design-For-Testability Techniques and Automation for 3d Ics
Authors:	李進福
Contributors:	電機工程學系
Keywords:	Three-dimensional integrated circuit (3D IC);through silicon via (TSV);testing;design-for-testability;3D DRAM;BIST;BISD;BISR;研究領域：電子電機工程類
Date:	2011-08-01
Issue Date:	2012-01-17 19:06:56 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	使用矽穿孔（through silicon via, TSV）之三維整合技術可以提供比二維技術好的優點。雖然已有不同三維積體電路（3D IC）製造技術被提出，但是在3D IC 可以進入量產之前，還有許多挑戰須克服。其中，一個重大挑戰是測試。因此，本三年期計畫將研發應用於3D IC 之關鍵測試技術。這些技術可分為四大類：1) 標準化測試介面；2) TSV 測試技術；3) 3D IC 測試規劃技術；及4)三維記憶體測試技術。在標準化測試介面方面，我們將研發以IEEE 11491. 及IEEE 1149.7 為基礎之邏輯與記憶體晶粒（die）之標準化測試介面。在TSV 測試技術方面，我們將針對TSV 之永駐（stuck-at）與串音（crosstalk）瑕疵研發自我測試、自我診斷及自我修復技術。。在3D IC 測試規劃技術方面，我們將研發用於pre-bond 測試與post-bond 測試之測試排程演算法。在三維記憶體測試技術方面，我們將研發一應用於三維記憶體之低測試pad 數自我測試技術、應用於3D DDR4 DRAM 之自我測試技術及應用於3D DRAM 之可自我調整 refresh 時間及熱感知自我測試技術。最後，我們將整合所開發之可測性設計與測試規劃技術成為一3D IC 可測性設計與測試規劃自動化平台。 The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This 3-year project will develop some key testing techniques for 3D ICs. These key techniques can be divided into three categories: 1) standardized test interfaces, 2) TSV testing, 3) 3D IC test planning methodologies, and 4) 3D RAM testing. For the standardized test interfaces, we will develop IEEE 1149.1 and IEEE 1149.7-based test interfaces for logic and memory dies to reduce the required test pads in pre-bond test phase. For the TSV testing, we will develop built-in self-test (BIST), built-in self-diagnosis (BISD), and built-in self-repair (BISR) techniques to cover the stuck-at and crosstalk faults in TSVs. For the test planning techniques, we will develop the pre-bond and post-bond test scheduling algorithms. For the 3D RAM testing, we will develop a BIST scheme for 3D DDR4 DRAMs, a low-pad-count BISD scheme for 3D RAMs, and a self-adaptive refresh and thermal-aware BIST scheme for 3D DRAMs. Finally, we will integrate the techniques shown above into a platform of 3D IC design-for-testability and test planning automation. 研究期間：10008 ~ 10107
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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