English  |  正體中文  |  简体中文  |  Items with full text/Total items : 69937/69937 (100%)
Visitors : 23281450      Online Users : 567
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/49657


    Title: 應用於三維積體電路之設計、自動化與測試關鍵技術-子計畫二:應用於三維積體電路之異質系統探索平台與電源規劃技術(I);Heterogeneous System Exploration Platform and Power Planning Techniques for 3d Ics
    Authors: 劉建男
    Contributors: 電機工程學系
    Keywords: 三維積體電路;異質整合系統;系統架構探索;電源傳輸規劃;研究領域:電子電機工程類
    Date: 2011-08-01
    Issue Date: 2012-01-17 19:06:59 (UTC+8)
    Publisher: 行政院國家科學委員會
    Abstract: 為了整合更多的電路在同一個晶片之中,運用矽穿孔(TSV)技術所發展的三維積體電路(3D IC)整合方式,是未來最被看好的方法之一,它可以將不同的晶粒(die)做垂直的堆疊,使得總體的連線長度縮短,傳輸頻寬提升,功率消耗降低,並有效減少晶片的面積。然而,要完成整個三維積體電路的系統,將會面臨許多之前不曾出現的難題,絕對需要一個新的系統設計方法以及相關的電腦輔助設計 (CAD)技術之配合,才有成功的機會。雖然目前已有許多針對三維積體電路之實體設計的CAD 研究正在進行中,但是對於三維積體電路的系統設計這個環節,卻比較少有人進行相關的研究。因此,在這個三年期計畫之中,我們希望能針對系統設計的需求,發展適合三維積體電路之異質整合 (heterogeneous)系統架構探索平台,並與其他子計畫搭配,將電源規劃(power planning)的考量也加入自動化的設計平台之中,以幫助設計者快速地完成三維積體電路系統的設計。若將不同特性的電路放置於不同的晶粒之中,再藉由三維積體電路的技術將它們整合成一個單一晶片,就可以很容易地實現異質整合的系統,然而,對設計者來說,如何確認這整個龐大的系統能夠正確運作,就變成了一個很大的挑戰。目前的系統層級(ESL)模擬環境,大部分都是針對以處理器為中心的數位系統做模擬,對於類比電路、記憶體電路等等非數位電路的功能區塊則較少研究,並無法支援三維積體電路所面臨的異質整合系統設計。因此,在這個三年期計畫中,我們將延續本研究群之前在類比電路模型上的成果,針對異質整合系統的不同組成區塊,研發自動化之行為模型產生器,並與子計畫四合作,針對異質整合系統建置系統層級的快速模擬平台,可以整合行為模型進行快速地系統模擬,並提供效能評估、功率消耗、雜訊影響、測試規畫等分析結果,以提供設計者足夠的資訊進行三維積體電路內的系統架構探索與最佳化。在三維積體電路的晶片之中,每個晶粒所使用的製程與需求的電壓可能都不相同,再加上垂直疊放晶片所帶來的額外複雜度,將會使得晶片內的電源傳輸規劃變成一個新的挑戰,必須在設計的初期就預做完善的規劃。因此,在本計畫之中,我們將與子計畫一攜手合作,研發自動規畫三維積體電路之電源輸送架構的最佳化技術,可以支援各晶粒不同電壓之需求,並找出最佳的電壓轉換電路配置方法。為了處理此種新式電源輸送架構所產生的電源雜訊,本計畫也將擴充系統層級的分析平台,加入全晶片之電源雜訊分析的能力,並與子計畫三合作,研發適用於三維積體電路之去耦(decoupling)電容設計自動化技術,以發展成一套完整的電源傳輸設計自動化平台,減少整個三維積體電路設計流程所需耗費的時間。In order to integrate more circuits into a single chip, the 3D IC integration based on through-silicon-via (TSV) is one of the possible approaches in the future. By vertically stacking different dies in a single chip, the total wire length can shortened, the signal bandwidth can be increased, the power consumption can be reduced, and the chip area can be reduced, too. However, designers will face many new challenges while implementing the 3D IC systems. A new design methodology and corresponding CAD techniques are absolutely required to solve those new design issues in 3D ICs. Although there are many researches on the CAD techniques for the physical design of 3D ICs, not too many works are discussing the system design of 3D ICs. Therefore, in this three-year project, we will try to develop a heterogeneous system exploration platform for 3D-IC systems. Co-working with other projects, we will also try to consider the power planning issues into the automatic design platform to help designers design the 3D-IC system in a short time. Using the 3D IC techniques, it is easier to implement a heterogeneous system by partitioning the circuits with different properties into different dies. For such heterogeneous systems, one of the tough issues is to verify the correctness of the whole system. Most existing ESL analysis environments focus on the processor-based digital systems only. Without the capabilities to analyze those non-digital blocks, such as analog circuits, memory circuits, etc., those ESL analysis tools cannot deal with the heterogeneous systems in 3D ICs. Therefore, in this three-year project, we will try to use our previous experience on analog behavior modeling to develop automatic behavioral model generator for different blocks in a heterogeneous system. With those behavioral models, we can develop a fast ESL analysis platform for heterogeneous systems to provide the information about performance evaluation, power consumption, noise effects, and testing planning of the whole system. Those important information can help designers to explore different system architectures and perform optimization while designing 3D IC systems. In a 3D-IC chip, the manufacturing process and required supply voltage may be different in different dies. In addition, the vertical integration in 3D ICs also contributes new challenges for the power delivery of 3D-IC systems. A complete planning is definitely required at early design stages to solve the power supply issues in 3D ICs. Therefore, in this three-year project, we will try to develop automatic optimization techniques for the power delivery architecture of 3D ICs to support the different supply voltage requirements and find a best allocation of voltage converters. In order to deal with the power supply noise (PSN) in the new power delivery architecture, the whole chip PSN analysis capability will also be added into the ESL simulation platform. With the PSN analysis results, we will co-work with other project to develop different automatic allocation techniques of decoupling capacitors for 3D ICs. Hope this design automation platform of the power delivery architecture can save considerable design time for 3D-IC systems. 研究期間:10008 ~ 10107
    Relation: 財團法人國家實驗研究院科技政策研究與資訊中心
    Appears in Collections:[電機工程學系] 研究計畫

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML335View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明