English  |  正體中文  |  简体中文  |  Items with full text/Total items : 66984/66984 (100%)
Visitors : 23023351      Online Users : 224
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/5186


    Title: 微波輻射計數位相關器之設計與實現;Desgin and Implement the Digital Correlator of Digital Total Power Microwave Radiometer
    Authors: 吳俊毅;Jiun-Yi Wu
    Contributors: 太空科學研究所
    Keywords: 數位相關器;微波輻射計;FPGA;Verilog;硬體描述語言;IC設計;Digital Correlator;Microwave radiometer;FPGA;Verilog;Hardware description language;IC design
    Date: 2005-09-28
    Issue Date: 2009-09-22 09:46:42 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 本篇論文主要在於探討36.5GHz微波輻射計之數位相關器的設計與實現,參考1999年Fischman文章中,由理論結果提出的類比數位轉換器解析度只需要2-3位元,即足以接近理想類比式微波輻射計的輸出特性。依據36.5GHz數位式微波輻射計設計規格中,於中頻中心頻率為500MHz,頻寬為20MHz,使用次諧波取樣(subharmonic sampling)技術,以六位元類比數位轉換器取樣頻率為40MHz,積分時間為0.5秒,進行數位相關器之設計與實現。 數位相關器主要架構由六位元平方器、三十二位元累加器、RS-232串列傳輸控制器與控制單元所組成,平方器使用改良式布斯乘法器、累加器使用十二位元前瞻進位加法器與二十位元計數器串接而成,主要目的在於提升運算速度,RS-232串列傳輸控制器與控制單元皆使用有限狀態機的設計結構。設計方式以Verilog硬體描述語言設計,使用FPGA(FLEX 10K100ARC240-1)實驗板實現,在接收程式設計以Borland C++ Builder設計,傳輸速率使用57600bps,可即時接收與控制數位相關器資料。 從以上數位相關器與接收程式的實現與量測,完成了數位相關器實現也具備與電腦介面的整合功能,未來目標朝著全系統量測以完成微波輻射計的原型機實現。 In this thesis, the digital correlator of a digital total power microwave radiometer at 36.5 GHz is designed and implemented. Fischman (1999) theoretically showed that just 2 or 3 bits for the A/D converter resolution are needed to maintain the performance of an ideal analog radiometer. According to the specification of the radiometer, the MF center frequency is 500MHz and its signal bandwidth is 20MHz. To design and implement the digital correlator, a subharmonic sampling technique is used to determine the sample frequency of the 6 bits A/D converter (40 MHz) and the integration time (0.5 s). The architecture of the digital correlator includes a 6-bit squarer, a 32-bit accumulator, a RS-232 UART and a control unit. The 6-bit squarer is designed by a modified Booth multiplier, and the 32-bit accumulator is designed by 12-bit Carry look-ahead adder and 20-bit counter. The purpose of the squarer and the accumulator is to improve the calculation speed. The RS-232 UART and the control unit are based on the finite state machine architecture. All of these components are designed using the Verilog hardware description language and implemented by a FPGA experimental board (Flex 10K100ARC240-1). The receiver program, implemented using the Borland C++ builder, can set the maximum transfer rate at 57600bps and can control and receive data from the correlator in real time. Finally the digital correlator and the receiver program are implemented. The digital correlator is successful to communicate with computer. Future work will involve the full system measurement to complete the prototype of the digital total power microwave radiometer at 36.5 GHz.
    Appears in Collections:[太空科學研究所 ] 博碩士論文

    Files in This Item:

    File SizeFormat
    0KbUnknown782View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明