A 6.4 Gbit/s Embedded Compression Codec for Memory-Efficient Applications on Advanced-HD Specification

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/51895

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/51895

Title:	A 6.4 Gbit/s Embedded Compression Codec for Memory-Efficient Applications on Advanced-HD Specification
Authors:	Tsai,TH;Lee,YH
Contributors:	電機工程學系
Keywords:	TECHNOLOGY;TVS
Date:	2010
Issue Date:	2012-03-28 10:09:46 (UTC+8)
Publisher:	國立中央大學
Abstract:	The embedded compression (EC) technique is applied to reduce the memory bandwidth and capacity in a display system. In this paper, the high-speed EC algorithm is proposed for advanced-HD specification. It mainly comprises three features: 1) the associated geometric-based probability model is developed to construct context-modeling mechanism without context-table; 2) develop content-adaptive Golomb-Rice code and geometric-based binary code as the entropy coding with minor order of context; and 3) provide the rate control mechanism to guarantee the saving ratio of memory bandwidth and capacity. With competitive coding efficiency, the computation-efficiency of the proposed EC algorithm is about 44% and 40% of FELICS and JPEG-LS. The proposed very-large-scale integration architecture of entire codec is implemented in TSMC 0.18-mu m 1P6M CMOS technology. Based on pixel-based parallelism and segment-based parallelism techniques, the encoding/decoding capability reaches Quad Fullhigh definition (QFHD) (3840 x 2160) at 30 Hz. The maximum throughput is as high as 6.4 Gbit/s. Furthermore, with multi-level parallelism, the performance can be extended to QHD (2560 x 1440) at 120 Hz and QFHD at 120 Hz for the double frame rate technique.
Relation:	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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