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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/51981


    Title: ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs
    Authors: Tseng,TW;Li,JF;Hsu,CC
    Contributors: 電機工程學系
    Date: 2010
    Issue Date: 2012-03-28 10:12:28 (UTC+8)
    Publisher: 國立中央大學
    Abstract: Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14N test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512 x 16 x 64-bit RAMs of which each RAM has one spare row and one spare column.
    Relation: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    Appears in Collections:[電機工程學系] 期刊論文

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