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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52010


    Title: A 0.18-mu m Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits
    Authors: Chang,HY;Liang,KH
    Contributors: 電機工程學系
    Keywords: LOW-NOISE AMPLIFIER;LOW-POWER;P-MOSFET;10 GHZ;MIXER;DESIGN;EXTRACTION;SYSTEMS
    Date: 2011
    Issue Date: 2012-03-28 10:13:13 (UTC+8)
    Publisher: 國立中央大學
    Abstract: A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the distributed resistances, and the inductances, are extracted from the measured S-parameters. In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is also evaluated with power sweep and load-pull measurements. In addition, a doubly balanced dual-gate mixer is successfully demonstrated using the proposed model. The measured results agree with the simulated results using the proposed device model for both linear and nonlinear applications. The advanced large-signal dual-gate CMOS model can be further used as an RF sub-circuit cell for simplifying the design procedure.
    Relation: IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
    Appears in Collections:[電機工程學系] 期刊論文

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