This study demonstrates a 6-GHz triangular-modulated spread-spectrum clock generator (SSCG) based on a fractional-N PLL in a 90-nm CMOS process. This paper presents a phase-rotating technique to create the fractional-N topology for the SSCG and implement spread-spectrum clocking (SSC) by modulating the fractional-N ratios. The proposed phase-rotating technique consists of virtual multiphase generation and the phase compensation approach. This technique effectively compensates the instantaneous timing error and shows the ignorable quantization error. Unlike the delta-sigma technique commonly used for SSCGs, the proposed SSCG realizes non-dithered fractional division ratios. In terms of SSC, this approach suppresses the RMS jitter to less than 1 ps, showing a significant improvement in the jitter performance in this work. The measured power attenuation of electromagnetic interference (EMI) is 16.12 dB, with a deviation of less than 0.5% (5000 ppm). Operating at a 6-GHz clock rate, the measured RMS jitter with and without the down-spreading spectrum are 0.77 and 0.71 ps, respectively. The chip core area is less than 0.55 x 0.45 mm(2) and the core power consumption is 27.7 mWat a supply of 1.0 V.