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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52021


    Title: A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy
    Authors: Tseng,TW;Li,JF
    Contributors: 電機工程學系
    Keywords: EMBEDDED MEMORIES;INFRASTRUCTURE IP;REPAIR;YIELD;DESIGN
    Date: 2011
    Issue Date: 2012-03-28 10:13:29 (UTC+8)
    Publisher: 國立中央大學
    Abstract: Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy-analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also proposed. Simulation results show that the proposed BIRA scheme can provide high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) for the RAMs with different fault distributions. Experimental results show that the hardware overhead of the BIRA design is only about 2.9% for an 8192 x 64-bit RAM with two spare rows and two spare columns. Also, the ratio of the BIRA analysis time to the test time is only about 0.02% if the March-CW test is performed. Furthermore, a simulation flow is proposed to determine the size of the 1-D local bitmap such that the BIRA algorithm can provide the best repair rate using the smallest-size 1-D local bitmap.
    Relation: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    Appears in Collections:[電機工程學系] 期刊論文

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