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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52023


    Title: A Novel Design of CAVLC Decoder with Low Power and High Throughput Considerations
    Authors: Tsai,TH;Fang,TL;Pan,YN
    Contributors: 電機工程學系
    Keywords: VIDEO CODING STANDARD;VLSI ARCHITECTURE;MPEG-4 AVC/H.264;H.264/AVC;COMPLEXITY;ENCODER;MEMORY
    Date: 2011
    Issue Date: 2012-03-28 10:13:32 (UTC+8)
    Publisher: 國立中央大學
    Abstract: This paper proposes a novel algorithm and its very large scale integration design for context-based adaptive variable length code (CAVLC) decoding. In order to improve throughput of CAVLC decoder, we propose two new methods, which are multiple level decoding (MLD) and nonzero skipping for run-before decoding (NZS). By performing parallel operations on the level decoder, MLD can decode two levels in one cycle at most situations, and NZS can produce several values of run-before in the same cycle. These two methods have the advantages of low complexity and regularity. The proposed architecture needs 141 cycles/macroblock. Moreover, the proposed CAVLC decoder can run at 33.5MHz to meet the real time requirement for 1920x1088 resolution. The power consumption for the 1920x1088 resolution is about 1.83mW. The operation frequency can be reduced about 29.1% to 71.5% compared with other architectures. With an aid on a lower operation frequency, it is suitable for many low power applications. The synthesis result shows that the gate count is 13175 gates, and the maximum frequency can archive 160 MHz.
    Relation: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    Appears in Collections:[電機工程學系] 期刊論文

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