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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52029

    Title: All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator
    Authors: Huang,HY;Liu,JC
    Contributors: 電機工程學系
    Date: 2011
    Issue Date: 2012-03-28 10:13:41 (UTC+8)
    Publisher: 國立中央大學
    Abstract: This work presented a 150-450-MHz, all-digital phase-locked loop (ADPLL) implemented in a 0.18 mu m CMOS process. The design utilizes bulk-controlled varactor and pulse-based digitally controlled oscillator (PB-DCO) providing a high timing resolution and a good jitter performance. The worst-case total locking time of the proposed ADPLL is 32 reference clock cycles. The divider used here divides by factors from 2 to 63. A test chip is implemented and verified. The RMS and peak-to-peak jitters are 6.7 and 44 ps, respectively, at 450-MHz. The peak-to-peak jitter is 2.0% at 450-MHz. When the multiplication of divider is varying at 150-MHz, the peak-to-peak jitters are less than 3.2%. The power consumption is 16.2-mW at 450-MHz. The core area of ADPLL is only 260 x 360 mm(2). This clock generator can be applied as re-usable silicon IP for system-on-chip (SoC) applications.
    Appears in Collections:[電機工程學系] 期刊論文

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