English  |  正體中文  |  简体中文  |  Items with full text/Total items : 66984/66984 (100%)
Visitors : 22985617      Online Users : 383
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52040


    Title: Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator
    Authors: Cheng,KH;Liu,JC;Chang,CY;Jiang,SY;Hong,KW
    Contributors: 電機工程學系
    Keywords: TO-DIGITAL CONVERTER;SUBPICOSECOND RESOLUTION;CMOS
    Date: 2011
    Issue Date: 2012-03-28 10:13:57 (UTC+8)
    Publisher: 國立中央大學
    Abstract: This paper proposes a 3-GHz built-in jitter measurement (BIJM) circuit to measure clock jitter on high-speed transceivers and system-on-chip (SoC) systems. The proposed BIJM circuit adopts a high timing resolution and self-calibration techniques. To eliminate process variation effects in 3 GHz systems, this study proposes an auto-calibration technique for the self-refereed circuit and other calibration techniques for the time amplifier (TA) and vernier ring oscillator (VRO), respectively. These calibration techniques can reduce the timing resolution variation of the vernier ring oscillator and the gain variation of the TA by 66% and 65%, respectively. This reduces the timing resolution variation of BIJM by 60%. Because the vernier ring oscillator and time amplifier achieve a small timing resolution, the BIJM circuit does not need an additional jitter-free reference signal using the self-refereed circuit. This study fabricated the BIJM circuit using the UMC 90-nm CMOS process. The BIJM circuit has a power consumption measuring 11.4 mW, and its core area is 120 mu m x 320 mu m. The BIJM circuit measured the Gaussian distribution jitter at a 1.8 ps timing resolution with a 3-GHz input clock frequency.
    Relation: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    Appears in Collections:[電機工程學系] 期刊論文

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML252View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明