Memory Built-In Self-Repair Planning Framework for RAMs in SoCs

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/52085

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52085

Title:	Memory Built-In Self-Repair Planning Framework for RAMs in SoCs
Authors:	Hou,CS;Li,JF;Tseng,TW
Contributors:	電機工程學系
Keywords:	REDUNDANCY-ANALYSIS;INFRASTRUCTURE IP;YIELD;SRAMS;SCHEME;FAULTS
Date:	2011
Issue Date:	2012-03-28 10:15:04 (UTC+8)
Publisher:	國立中央大學
Abstract:	Built-in self-repair (BISR) techniques are widely used to enhance the yield of random access memories (RAMs) in a system-on-chip (SoC) which typically consists of hundreds of RAMs. Hence, many BISR circuits may be needed in a such SoC. Effective techniques for planning these BISR circuits thus are imperative. In this paper, we propose a memory BISR planning (MBiP) framework for the RAMs in SoCs. The MBiP framework consists of a memory grouping algorithm for selecting RAMs which can share a BISR circuit. Then, a test scheduling algorithm is used to determine the test sequence of RAMs in a SoC under the constraint of test power. Finally, a BISR scheme allocation algorithm is proposed to allocate different BISR schemes for the RAMs under the constraints of the results of memory grouping and test scheduling. Simulation results show that the proposed MBiP can effectively plan the BISR schemes for the RAMs in a SoC. For example, about 22% area reduction can be achieved by the BISR schemes planned by the proposed MBiP framework for 50 RAMs under 1.5 mm distance constraint and 350 mW test power constraint in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit).
Relation:	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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