SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/52100

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52100

Title:	SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories
Authors:	Tseng,TW;Li,JF
Contributors:	電機工程學系
Keywords:	DESIGN;BIST;CHALLENGES;SYSTEMS
Date:	2011
Issue Date:	2012-03-28 10:15:27 (UTC+8)
Publisher:	國立中央大學
Abstract:	Variability in transistor performance will continue to increase with the scaling of technology. Transistors are more and more unreliable. Also, the noise-tolerant capability of circuits is less and less robust. To avoid the loss of yield and fault coverage, the design-for-testability circuit must be designed to be noise-tolerant. This paper presents a soft-error tolerant built-in self-test (SETBIST) design for random access memories (RAMs). Some soft-error-mitigation (SEM) techniques are proposed to enhance the soft-error immunity of the instruction register, March operation generator, address generator, and data background generator. Experimental results show that the area overhead of the SETBIST is only about 1.1% for an 8K x 64-bit SRAM. Analysis results show that the SETBIST can effectively tolerate soft errors. We also use FPGA demonstration board to verify the SETBIST scheme.
Relation:	JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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