生物醫療晶片往往具有低功耗和低電壓的特性，因此才能達到可攜式、可植入的設計目的。本論文主旨在實現一個低功率數位濾波器設計，此數位濾波器可適用於生醫訊號處理之低電壓、低功耗、低面積的三角積分類比數位轉換器，將最占面積、最耗電的數位降頻濾波器加以改進，並成功的將其實現，以利於達成可攜式的生醫儀器之輕薄短小與維持電池長效性的要求。可適用於生醫訊號處理之三角積分類比數位轉換器(ADC)的前級電路是採用三角積分調變器(SDM)，該SDM的晶片是採用TSMC 0.18μm 1P6M CMOS技術來實現。其訊號寬為10KHz，取樣頻率為2.56MHz，超取樣率(OSR)是128，而信號與訊號失真比(SNDR)可達到75.75dB，且高於10位元解析度。而後端電路為本篇論文所設計的數位降頻濾波器，採用三級不同階數的濾波器所串接組成。第一級CIC濾波器使用直接式(direct form)架構和多相位分解(polyphase decomposition)表示法，並於文中提出濾波器係數優化搜尋法，藉此搜尋法去找出最少的硬體使用資源。第二級的CIC補償濾波器和第三級的Half-Band濾波器，則是採用CSD (canonic signed digit)和Variable wordlength的設計方法，藉此有效的降低硬體面積和功率消耗。本論文的數位濾波降頻器經由FPGA的硬體實現，其信號雜訊失真比(SNDR)為73.98dB，且高於10位元解析度。最後，使用TSMC 0.13μm的製程去進行晶片設計，在完成APR (auto placement & route)的設計步驟後，可以得到的晶片面積為0.46mm*mm，預估之功率消耗為339μW。Low power consumption and low power supply voltage are the basic requirements of biomedical chip, especially in portable and implementable biomedical systems. In the study, we would like to realize an efficient and low power consuming Sigma-Delta Analog/Digital converter. For the reason we need to improve the digital filter part, which is the mostly area-required and power-consumed part to satisfy portable and long battery lifetime requirements of biomedical instruments. The previous stage of Sigma-Delta Analog/Digital converter is Sigma-Delta Modulator (SDM) with TSMC 0.18μm 1P6M CMOS technologies. The signal bandwidth is 10 KHz and its clock rate is 2.56 MHz i.e. the over-sampling ratio (OSR) is equal to 128. Besides, it can achieve 75.75dB signal-to-noise and distortion ratio (SNDR), and higher than 10 bits resolution. The digital back end is a decimator which is composed of three stages of FIR filter with different taps. The Polyphase decomposition and direct form implementation approaches are applied in the Cascaded Integrator-Comb (CIC) filter design to achieve low power target. Furthermore, the “search method for direct form implementation” is also proposed to minimize circuit area. The canonical signed digit (CSD), common sub-expression sharing (CSE) and Variable wordlength approaches are applied in the CIC compensation filter and Half-Band filter to achieve low power and minimize circuit area.This design is implemented on Lattice FPGA evaluation board. It can achieve 73.98dB SNDR and 12 bits resolution. The proposed design was simulated with TSMC 0.13μm CMOS process. The power consumption is 339μW and chip area is 0.46mm*mm.
