| 摘要: | 當製程邁入奈米(nanometer)時代，元件尺寸(device size)也跟著不斷的縮小，使得製造過程的參數漂移現象，開始明顯的影響到整個晶片的效能(performance)及良率 (yield)，因此，良率導向設計方法(Design for Yield, DFY)，在近年來變成很熱門的話題，希望在電路設計的初期，就能把製程偏移(process variation)的現象考慮進來，以提升良率、降低成本。DFY 相關的技術，在數位電路的應用上已經研究了一陣子，但對於類比電路來說，則一直缺乏系統化的DFY 技術可以協助，主要還是依賴設計者的經驗來解決。可是，參數漂移對於類比電路的影響，其實比數位電路要來得嚴重很多，因此，在這個三年期計畫之中，我們希望能利用之前發展混合訊號行為驗證平台的經驗，以類比電路行為模型為基礎，發展考慮良率的設計流程及相關的自動化技術，幫助設計者在早期評估可能的良率結果，進而提供良率最佳化(yield optimization)的電路設計策略。第一步是進行製程偏移的影響分析，傳統的分析方法主要是透過HSPICE 模擬器進行幾百次或幾千次的電晶體階層(transistor level)模擬，再推估元件參數變動對於整個晶片效能的影響分佈，然而，數百次這樣的低階模擬實在太過耗時。因此，在這個三年期計畫之中，我們將試著延伸之前發展的類比行為模型，發展一個行為層級的蒙地卡羅分析平台，以快速地完成類比電路的製程偏移分析，希望能將數十天的模擬過程縮短至數個小時之內完成。第二步是優化類比電路的容忍度。若是分析出來的良率不佳，設計者往往面臨不知從何下手修改的窘境。因此，在這個三年期計畫的中期，我們將試著利用第一年所製作的良率分析平台，從那些統計分析的結果之中，歸納出一些有用的資訊，作為改善電路的參考。之後，再從行為模型的參數調整入手，利用行為模型快速模擬的特性，在很短的時間內對多種可能的調整方案做出評估，找出良率較佳的nominal point，進而達到改善類比電路良率的目標。第三步是發展自動化設計與分析平台。在SOC 的設計之中，使用類比合成的工具快速地產生符合系統規格需求的analog IP，已變成了最有效率的設計方法。然而，過去的自動化方法沒有考慮製程參數變動的情況，因此，在本計畫的後期，我們將試著把良率導向的設計概念整合在自動化設計的流程中，與子計劃一攜手合作，開發一套簡單的方法，快速地產生一個滿足設計規格的nominal design，作為良率調整的起點，再運用前兩年所開發的方法來微調尺寸，以快速產生高良率的類比IP。 ; With nanometer semiconductor technology, the device size is continuously shrinking. Currently, the device parameter variations have more and more impacts on the chip performance and yield. In order to solve this issue, design-for-yield (DFY) techniques are getting popular, which try to consider the process variation effects in early design stages. The DFY techniques for digital circuits have been studied for several years. However, for more sensitive analog circuits, no systematic DFY techniques are available now. Therefore, in this three-year project, we will try to use our previous experience on mixed-signal behavioral modeling to develop several DFY techniques for analog circuits. Based on analog behavioral models, we can provide fast yield analysis and optimization methodologies and develop an automation platform with yield consideration. The first step is analyzing the process variation effects. Traditional approaches select hundreds of samples with different parameter values to perform transistor-level simulations and observe the output performance under process variation. However, repeating hundreds of transistor-level simulation is often too expensive. Therefore, in this three-year project, we will try to extend our analog behavioral models to reflect device parameter variations. Based on those variation-aware behavioral models, we can develop a behavior-level Monte Carlo analysis platform to obtain the impacts of process variations in a short time. The second step is optimizing the circuit tolerance to process variation. If the results of yield analysis are not good, designers may have no idea about how to modify the circuit for better yield. Therefore, in this three-year project, we will try to provide some improving suggestions from the data of yield analysis. By adjusting the parameters in the behavioral models, we can perform fast simulations to evaluate many different adjustments and find a nominal point with better yield. Hope it can offer designers better suggestions very quickly to improve design yield and save considerable design time. The third step is developing an analog design automation platform with yield consideration. Although analog synthesis has become an efficient design methodology for SOC designs, the process variation effects are not considered in traditional automation algorithms. Therefore, in this three-year project, we will try to integrate our yield improving methods into the analog design automation platform. Using the design experience from other subprojects, we will develop a fast method to generate an initial design that satisfies all design specifications at the nominal point. Then, the proposed yield analysis and improving methods can be applied to improve the yield of analog IPs. Hope this platform can save considerable design time and improve the overall yield of SOC designs. ; 研究期間 9708 ~ 9807 |
