適用於類比電路之隱含式良率改善技術之研究;On Implicit Design Centering Approach for Analog Circuits

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/57428

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/57428

Title:	適用於類比電路之隱含式良率改善技術之研究;On Implicit Design Centering Approach for Analog Circuits
Authors:	劉建男
Contributors:	中央大學電機工程學系
Keywords:	電子電機工程類;良率導向設計方法;製程偏移;類比行為模型;設計中心化;良率最佳化;Design-for-Yield;Process Variation;Analog Behavioral Model;Design Centering;Yield Optimization
Date:	2009-09-01
Issue Date:	2012-10-01 15:20:37 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	當製程邁入奈米(nanometer)時代，元件尺寸(device size)也跟著不斷的縮小，使得製造過程的參數漂移現象，開始明顯的影響到整個晶片的效能(performance)及良率 (yield)，因此，良率導向設計方法(Design for Yield, DFY)，在近年來變成很熱門的話題，希望在電路設計的初期，就能把製程偏移(process variation)的現象考慮進來，以提升良率、降低成本。DFY 相關的技術，在數位電路的應用上已經研究了一陣子，但對於類比電路來說，則一直缺乏系統化的DFY 技術可以協助，主要還是依賴設計者的經驗來解決。可是，參數漂移對於類比電路的影響，其實比數位電路要來得嚴重很多，因此，在這個計畫之中，我們希望能利用之前發展混合訊號行為驗證平台的經驗，以類比電路行為模型為基礎，發展一套針對類比電路的良率導向設計流程，希望能在電路設計階段修改電路，在較高的設計階層將電路的標稱設計(nominal design)移動到較不受製程變異現象影響的位置，達到提升電路生產良率的目的。設計中心化(design centering) 是一種最常被使用在設計良率最佳化(yield optimization)的技術，藉由修改標稱設計點的位置，讓大部分效能模擬的樣本點，均落在允許之參數設計區間(acceptable design region)之中，以獲得更高的設計良率。然而，傳統的作法必需要預先設定電路的設計限制，並建立繁複的數學方程式來連結電路規格與所有的元件參數之關係，以定義出可行性參數區間的邊界，對較為複雜的類比電路而言，是一件相當困難的事情。如同先前的研究文件中所記錄，這個步驟已經成為整個良率優化流程之中的最大的瓶頸。因此，本計劃提出一個完全不同的良率優化設計方式，無須定義複雜的可行性參數區間之邊界，而是重複使用既有的良率模擬結果，再利用統計分析的方法與力學模型的輔助，找到設計標稱點應該移動的位置來改善良率。這一種隱含式(implicit)的良率優化方法，在不需要描繪可行性參數區間之邊界的前提下，大大地節省了整個良率優化流程所需的時間，即使是較為複雜的類比電路，也能夠有效率地去修正設計標稱點，達到良率優化的目的。為了將計算出來的較佳標稱點實現出來，本計劃也將研發階層式之參數調整技術，將此標稱點所對應的行為階層參數值(behavioral-level parameter)計算出來，再利用現成的一些參數調整工具，就可以快速地找出此標稱點所對應的元件尺寸修改方案，協助電路設計者能更有效率的改良設計，進而提升電路之設計良率。在本年度的計畫中，我們將會試著以一個大型的鎖相迴路(PLL)電路為實例，開發這個流程之中所需的各種演算法，並實際驗證所提出之方法的效果與可行性。 ; With nanometer semiconductor technology, the device size is continuously shrinking. Currently, the device parameter variations have more and more impacts on the chip performance and yield. In order to solve this issue, design-for-yield (DFY) techniques are getting popular, which try to consider the process variation effects in early design stages. The DFY techniques for digital circuits have been studied for several years. However, for more sensitive analog circuits, no systematic DFY techniques are available now. Therefore, in this project, we will try to use our previous experience on mixed-signal behavioral modeling to develop DFY techniques for analog circuits. Based on analog behavioral models, a nominal point moving algorithm is proposed to reduce the impacts of process variation on analog circuits at early design stage. Design centering is one of the popular yield optimization techniques. Its aim is to find a nominal design that makes most simulation samples under process variation fall into the acceptable design region. Conventional design centering techniques often use a geometric approach to locate the feasible design region first. However, complicated formulas and numerous design constrains are often required to describe the boundaries of feasible design regions. For complicated analog circuits, finding the feasible region or its partial boundaries within the circuit space is extremely complicated even for a given circuit topology. Therefore, a novel implicit approach is proposed in this project to improve the user-given analog circuits toward better yield. The key idea is reusing the yield analysis data and applying the mechanical work-energy theorem to determine the new nominal point based on the Pass/Fail distributions. Since exploring the feasible region is not necessary in this boundary-less approach, the computation time of the yield enhancement flow can be significantly reduced, which enables this approach to deal with complicated analog circuits. A hierarchical sizing approach is also proposed to synthesize the new nominal design from performance level to behavior level. With the corresponding behavioral parameters, any existing approach can be applied to determinate the device sizes of the new nominal point, which helps designers improve their designs more easily. In this year, a complicated phase-locked-loop circuit will be used as a case study to develop the required algorithms in the proposed yield enhancement flow. The feasibility and improvements will also be verified using this large case. ; 研究期間 9808 ~ 9907
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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