MIPI CSI-2 接受器的低功率設計及其硬體實現;Low Power MIPI CSI-2 Receiver Design and Hardware Implementations

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Title:	MIPI CSI-2 接受器的低功率設計及其硬體實現;Low Power MIPI CSI-2 Receiver Design and Hardware Implementations
Authors:	呂岳全;Lu,Yueh-Chuan
Contributors:	通訊工程學系在職專班
Keywords:	Camera Serial Interface (CSI);MIPI;低功率設計;硬體實現;降低功耗;Camera Serial Interface (CSI);Hardware Implementation;Low Power;MIPI
Date:	2013-01-25
Issue Date:	2013-03-25 16:15:16 (UTC+8)
Publisher:	國立中央大學
Abstract:	MIPI協會制訂了低功率和高速的CSI-2(Camera Serial Interface 2)規格，CSI-2主要提供圖像感測器與影像處理端的資料傳輸介面。本篇論文提出CSI-2接收端的低功率硬體架構設計。我們採用一個8位元組並列CSI協定層(protocol layer)架構，此架構利用除頻器產生可調整的時脈，針對不同數目資料通道(Data Lane)給予不同的時脈，配合所提出8位元組通道合併層(Lane merger layer)，不僅可以降低頻率，且可以降低動態功率的消耗。此外，再加上一個8位元組CRC，可以讓整個CSI協定層在使用4條通道並且每一條通道資料傳輸率為1Gb/s(最大資料傳輸率4Gb/s)時操作在62.5MHz，在不影響資料傳輸率之下讓數位邏輯的運算時間由8ns增加為16ns，如此，可以降低CSI協定層的操作電壓，並達到降低功耗的目的。本篇架構是以TSMC 0.13μm 標準元件庫，在頻率125 MHz下合成出32.7 K的邏輯閘數量，驗證結果顯示，我們使用最大資料傳輸率4Gb/s在實際4通道CSI-2接收端IC上所量到的所有邏輯功率與參考文獻相比，可節省36%~43%的功耗。MIPI Alliance standard for CSI-2 (camera serial interface 2) provides the image sensor a normal, low power, high speed, and low cost interface that supports a extensive range of imaging solutions for mobile phone, pc-camera and vehicle video recorder devices. This thesis proposes the MIPI CSI-2 Receiver architecture for hardware implementations. We further adopt an 8-Byte parallel CSI protocol layer framework which provides a scalable clock by multi-Lane configurations for one, two or four lanes with an 8-Byte Lane merger layer. It not only reduces the operating frequency, but also reduces the dynamic power consumption. In addition, we propose an 8-Byte CRC. The CSI protocol layer can operate 4 data Lanes with 1Gb/s per data Lane (with the maximum rate of 4Gb/s) at 62.5 MHz. The proposed architecture increases logic operations from 8ns to 16ns without throughput degradation. Therefore, the supply voltage (1.2V) can be reduced and the power consumption can also be reduced.The architecture is implemented by TSMC 0.13μ CMOS technology and the total gate count is 32.7K at a clock frequency of 125 MHz. The results show that more than 36%~43% of logic power measured in chip can be saved while comparing with the literature.
Appears in Collections:	[Executive Master of Communication Engineering] Electronic Thesis & Dissertation

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