在本論文中，將提出一個建構於SOI基板上並與45°矽微反射面和矽波導整合之5-Gbps光學連接模組。此模組中，45°微反射面的建構是利用具等向性的濕蝕刻製程，於(100)晶向面的SOI晶圓之光子元件層上製作。其中，面射型雷射陣列和光偵測器陣列封裝於SOI晶圓之矽基板層的上面。而透過一次微影蝕刻的手法將45°微反射面與波導整合在SOI晶圓上，將可實現三維光路的建構。此三維光路首先由面射型雷射發射雷射光，透過45°微反射面耦合進波導中，再由另一個45°矽微反射面將光反射至光偵測器。 根據光學模擬結果顯示，本論文設計出之模組的光學效率可達67.4 %，而經由實際量測製程出來之模組，本模組的光學效率可達67 %。而且雷射和光偵測器在光學效率為1 dB時的位移容忍度皆可大於24 μm。證實了本論文所設計之光學平台可適用於雷射和光偵測器等主動元件的整合。 在模組的高頻傳輸能力上，本模組在未加接收端驅動IC之情況下，供給10 mA之電流源於面射型雷射並操作在5 Gbps的傳輸速率時，眼圖眼高為28.8 mV、抖動為25.51 ps、訊雜比可達8.1，而且眼圖訊號在其眼睛邊際 (Eye margin) 內是非常乾淨。本模組在加入接收端驅動IC後，眼圖的表現會有劇烈的提升。同樣供給10 mA之電流源於面射型雷射並操作在5 Gbps的傳輸速率時，眼圖眼高為228 mV、訊雜比可達13.81，其訊號之清晰程度有明顯的增加，而抖動為40.21 ps仍適用於5-Gbps的傳輸速率。而經過誤碼率的量測顯示，當雷射之驅動電流降至4 mA時，誤碼率仍能小於10-12等級。因此證明了本模組在5 Gbps的傳輸速率時具有較低的功耗。In this thesis, we proposed an intra-chip 5-Gbps optical interconnect module based on a silicon-on-insulator (SOI)-based substrate with silicon waveguides terminated with 45° micro-reflectors. The 45° slants of proposed waveguide are fabricated on the device layer of (100)-oriented SOI wafer using anisotropic wet etching. The vertical-cavity-surface-emitted-laser (VCSEL) array and the photo-detector (PD) array are assembled on the substrate layer of SOI wafer. The three-dimensional guide-wave path is realized by the 45° micro-reflectors monolithically integrated on the silicon waveguide. The laser beam emitting from the VCSEL array is coupled into the waveguide via a 45° micro-reflector, propagates along the waveguide, and then is coupled into the PD via another 45° micro-reflector at the output port.According to the optical simulated and experiment results, the optical efficiency along the VCSEL-waveguide-PD path of proposed module is 67%. Its 1-dB alignment tolerance of assembling a VCSEL or PD chip is as larger as 24 μm. It demonstrates that the optical characteristics of proposed guide-wave configuration on SOI wafer would facilitate the assembly of active devices.The high-frequency modulation of active devices is also studied at the fabricated modules. As the VCSEL array is biased at 10 mA, without an amplifier IC at the receiver side, the clear eye diagram with a eye height of 28.8 mV, a jitter of 25.51 ps, and the signal-to-noise ratio of 8.1 is demonstrated at the data rate of 5 Gbps. With the assistance of amplifier IC at the receiver side, the performance of eye diagram can be improved dramatically. Its eye height of 282 mV and the signal-to-noise ratio of 13.81 are demonstrated at the same biased condition of 10 mA. A jitter of 40.21 ps suitable for the data rate of 5 Gbps is obtained at such improved eye height. The 5-Gbps error-free performance of receiver side is also achieved at the level of 10-12 even the VCSEL is biased at 4 mA. The experiment data verifies the proposed intra-chip module can be operated at 5 Gbps with a low power consumption.
