應用於三維記憶體之可靠度增強技術;Reliability-Enhancement Techniques for TSV-Based 3D RAMs

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題名:	應用於三維記憶體之可靠度增強技術;Reliability-Enhancement Techniques for TSV-Based 3D RAMs
作者:	張立蓉;Chang,Li-Jung
貢獻者:	電機工程學系
關鍵詞:	三維記憶體;可靠度;錯誤更正碼;3D RAM;ECC;Reliability
日期:	2013-01-27
上傳時間:	2013-03-25 16:18:40 (UTC+8)
出版者:	國立中央大學
摘要:	使用穿矽穿孔 (TSV) 的三維整合技術是目前新興的電路設計技術。其中，三維隨機存取記憶體是三維整合技術中主流的應用。在三維記憶體之中，可靠度和良率是兩個主要的挑戰。在動態記憶體 (DRAM) 中的資料保存時間是一潛在的可靠度議題。動態記憶體中的資料保存時間取決於其溫度，若動態記憶體內的溫度導致記憶體單元的資料保存時間變短，則可被視作有一個軟錯誤。雖然可藉由提高更新頻率來解決資料保存問題，但其功耗也相對增加，使資料保存問題更加惡化。錯誤更正碼技術可減輕由於溫度帶來的可靠度問題。典型的錯誤更正碼技術提供記憶體中每個字元相同的修復能力。由於三維記憶體中每個晶粒和通道間的溫度差異很大，此方法並不能有效的適用於三維記憶體。在本論文中，我們提出了一個在三維記憶體中根據其錯誤率，增強可靠度並有效利用面積的錯誤更正碼機制。此機制可使記憶體中的每一區塊有各自相對應的修復能力，且達到面積與可靠度的最佳化。此外，我們同時提出一個動態調整的錯誤更正碼機制。我們提出了一個方法來評估三維記憶體中的每一個記憶體區塊的軟錯誤率。此動態調整的錯誤更正碼機制可根據記憶體區塊中的軟錯誤率，動態地調整錯誤修復能力。最後，我們提出了一個三維記憶體中可靠度和良率的評估平台。該平台可模擬三維記憶體中的記憶體和矽穿孔良率，並可評估三維記憶體中的可靠度。Three-dimensional (3D) integration technology using through-silicon via (TSV) is an emerging integrated circuit design technology. 3D random access memory (RAM) is one popular application of 3D integration technology. Reliability and yield are two challenges for designing and implementing 3D RAMs. Data retention may result in reliability issue when a dynamic random access memory (DRAM) is used in ?eld, since the data retention time of DRAMs is related to their temperature. If the temperature causes that the data retention time of a DRAM cell is not long enough, then the DRAM cell can be regarded as it has a soft error. Although increasing refresh frequency is one approach to resolve data retention problem, the increased power consumption worsens the issue of data retention. Error correction code (ECC) technique can mitigate the reliability issue caused by temperature. Typical ECC techniques provide ?xed correction capability for each word of a RAM, which are not effective for 3D RAMs due to the difference of thermal distribution of different dies and channels is large.In this thesis, we propose an area and reliability ef?cient-ECC scheme (ARE-ECC) for enhancing the reliability of 3D RAMs according to its error rate. The ARE-ECC scheme makes each memory block have its corresponding correction ability such that the area cost of parity bits and the reliability are optimized. Furthermore, a dynamically adaptive ECC (DA-ECC) scheme is also proposed. A simple approach is used to estimate the soft error rate of each memory block in a 3D RAM. Then, the DA-ECC scheme can dynamically change the error correction ability for each memory block according to the soft error rate of the memory block. Finally, a reliability and yield evaluation platform is proposed to evaluate the reliability and the yield of 3D RAMs. The platform can simulate the yield of 3D RAMs and TSVs. It also can evaluate the reliability of 3D RAMs.
顯示於類別:	[電機工程研究所] 博碩士論文

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