智慧型感測器網絡嵌入式硬體設計和實作; Embedded Hardware Design and Implementation of Smart Sensor Network

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題名:	智慧型感測器網絡嵌入式硬體設計和實作;Embedded Hardware Design and Implementation of Smart Sensor Network
作者:	郭星辰;Xingchen,Guo
貢獻者:	資訊工程學系
關鍵詞:	智慧感測器;智慧感測器網絡;硬體化;Modbus;嵌入式;FPGA;Smart Sensor;Smart Sensor Network;Hardware;Modbus;Embedded;FPGA
日期:	2013-07-03
上傳時間:	2013-08-22 12:11:47 (UTC+8)
出版者:	國立中央大學
摘要:	現有的智慧感測器系統常缺乏對多感測器的有效管理機制，因此導致處理器負擔大、工作效率低並且耗電量大；而基於處理器的現場總線協議和IEEE1451的智慧感測器開發正面臨即時性、可靠度和硬體成本等多重挑戰。本論文提出一個創新的智慧感測器網路架構，可以有效降低功耗、提高即時效能，並且具有更佳的感測器管理性能。系統包含全硬體化的智慧感測器節點、智慧感測器網路閘道器和基於C++builder的客戶端智慧感測器網路監控程式。我們所設計的系統符合智慧感測器定義的非線性校正、自補償、自檢、自診斷，同時進一步滿足智慧感測網路定義的感測器新增拔除、訊號擷取、故障偵測、模式控制、自動配置等功能。系統中以硬體化的Modbus模組為智慧感測器網路通訊基礎，另外採用CRC校驗、ARQ和漢明碼糾錯相配合的機制，以增進即時通訊的可靠度。本研究利用MIAT嵌入式硬體設計方法論進行所有功能模組的嵌入式硬體實作，可提供智慧感測網路的最高性能。此外，系統鮑率、Modbus功能碼和系統模組都可以方便調整並重新配置，兼顧了系統性能和靈活性。最後我們所實現的FPGA雛型系統在使用Altera Cyclone III-C25 FPGA和利用杜邦線短距離通訊的條件下，最高鮑率可達7.06Mbps，網路節點的響應時間為73.8us，網路資料傳輸成功率100%，無資料丟失現象，符合實時性和可靠性的系統需求。 Existing smart sensor system often lacks effective management mechanisms for multi-sensor system, resulting in a large burden on the processor, low efficiency and high power consumption while it’s difficult for smart sensor based on processor-based fieldbus protocol and IEEE1451 to achieve the goal of real-time, reliability, low-cost and so on. This paper presents an innovative intelligent sensor network architecture that can effectively reduce power consumption, improve real-time performance, and has a better management performance. This system consists of smart sensor nodes, smart sensor network gateway, both hardware realized , and a client monitoring program base on C++ builder. The system we designed meets the definition of smart sensor, such as non-linear calibration, self-compensating, self-inspection and self-diagnosis. What’s more, this system further meets the definition of smart sensor network, like nodes added detection, nodes removal detection, signal acquisition, fault detection, mode control, ID configuration. System uses Modbus hardware modules as the network communication infrastructure. In addition, we adopted the CRC, ARQ and Hamming code error correction mechanism to improve the reliability of real-time communication. In this study, we used Hierarchical Robotic Discrete-Event Modeling for the hardware implementation of all embedded functional modules. Additionally, the baud rate, Modbus functions and hardware modules can be easily adjusted and reconfigured, raising system performance and flexibility. Finally, we implemented FPGA prototype system by using Altera Cyclone III-C25 FPGA and DuPont lines. Under this short-range communication condition, the maximum system baud rate speeds up to 7.06Mbps, the node response time is only 73.8us, and data transfer success rate achieves 100%, with no data losing phenomenon. The system is in line with real time and reliability of system requirements.
顯示於類別:	[資訊工程研究所] 博碩士論文

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