研究期間：10208~10307;For more than 40 years, the integrated circuit industry has followed a steady path of constantly shrinking device geometries and increasing chip size, commonly referred to as “Moore’s Law.” However, continued downscaling of CMOS transistors faces immense challenges as device miniaturization does not necessarily yield performance enhancement. Novel materials or device structures are therefore being actively explored to improve the transistor performance. Recently, Si1-x-yGexCy semiconductor alloys and strain engineering have attracted intensive research interest because they offer enhanced carrier mobilities and more functionalities for the state-of-the-art electronics and optoelectronics. In this project, we propose to fabricate a variety of strained substrates with the use of oxidized porous Si as stressor. We expect to create (1) highly strained-Si substrates with tensile strain larger than 2.5%, (2) SiGe virtual substrates with Ge concentration more than 50%, and (3) tensile-strained-Si/compressive-strained-SiGe composite substrates. We also develop the Micro-Raman measurement technology to effectively characterize and analyze the patterning-induced asymmetric relaxation in nanoscale patterned substrates. New metal silicides/germanides are also explored in this project for integration with highly strained or high-Ge-concentration substrates. The influences of metal silicidation, such as Ge segregation and thermal stress, on nanoscale patterned heterostructures would be systematically investigated. To verify the feasibility and integration of the developed materials, we also develop the fabrication process and study the performance of strained-Si nanowire FETs. Finally, we develop silicide/germanide Schottky barrier diodes based on nanoscale patterned heterostructures and their Schottky barrier heights will be characterized. These results will provide useful information for fabricating high-mobility devices and integrating main-project enhancement technologies developed for advanced CMOS.
