用於二維與三維系統晶片中記憶體之可靠度及良率改善技術;Reliability and Yield-Enhancement Techniques for Memories in 2d/3d System Chips

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/63058

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/63058

Title:	用於二維與三維系統晶片中記憶體之可靠度及良率改善技術;Reliability and Yield-Enhancement Techniques for Memories in 2d/3d System Chips
Authors:	李進福
Contributors:	國立中央大學電機工程學系
Keywords:	電子電機工程
Date:	2012-12-01
Issue Date:	2014-03-17 14:18:01 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	研究期間：10108~10207;With the advent integrated circuit (IC) technology, there are two major trends in the future of IC designs. One trend is to design advanced system-on-chip (SOC) following the Moore's Law. Another trend is to design a system chip with the three-dimensional integration technology using through-silicon vias (TSVs), we call the system chip as 3D IC. Undoubted, memory is a key component in either the SOC or the 3D IC. Furthermore, memories in these two types of ICs usually represent a significant portion of the chip area. Therefore, efficient reliability and yield-enhancement techniques should be developed for the memories in SOCs and 3D ICs. In this three-year project, we will develop effective test, yield-enhancement, and reliability-enhancement techniques for variation-tolerance SRAMs, 3D RAMs, and heterogeneous memories. Also, we will develop effective reliability-enhancement techniques for 3D DRAMs. Finally, we will develop a reliability and yield-enhancement design automation platform for heterogeneous memories.
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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