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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/63068

    Title: 良率導向之類比陣列區塊電路自動產生器(III);Yield-Aware Automatic Generator for Analog Regular Array Blocks((Iii)
    Authors: 陳竹一;梁新聰
    Contributors: 國立中央大學電機工程學系
    Keywords: 電子電機工程;資訊工程;硬體工程;資訊科學;軟體
    Date: 2012-12-01
    Issue Date: 2014-03-17 14:18:15 (UTC+8)
    Publisher: 行政院國家科學委員會
    Abstract: 研究期間:10108~10207;This project “Yield-aware Automatic Generator for Analog Regular Array Blocks(III)” is a continuous project of “Yield-aware Automatic Generator for Analog Regular Array Blocks(II).” In this sub-project, it aims to address the impact of device correlation on the yield enhancement of mixed-signal/analog integrated circuits. The statistical correlation of device parameters depends on spatial locations. Thus, the relationship between correlation and variation of device matching or mismatching can be modeled according to their relative placements. For analog regular array blocks, traditionally, the layout placement of a matching pair of devices is performed by the principle of comment centroid. It is to propose a novel design methodology for device allocation in early design stage by using the capability of homogeneous isotropic random (HIR) spatial correlation. The advanced virtual placement (AVP) is a physical-level placement that can be generated, based on process design kit (PDK), early in the design cycle, in minutes, by circuit designers who are not layout experts. Today, an engineer who wishes to study the physical effects of an analog design must wait until the layout designer has finished the layout, which could take days or weeks. To move to more advanced process nodes, it will be more important than ever to have an accurate analog layout early in the design cycle. It is to explore how the circuit performance is affected by the spatial correlation in advanced technology and to improve the design yield. Accordingly, an automatic variation/yield-aware analog-array-block place-and-route platform is developed in order to accommodate to the need of design for manufacturability in a nanometer technology era. The generated block layout is also put into the P-cells in PDK as for re-use and system integration later. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed-up the time to market for high-speed, high-precision, and high yield of mixed-signal IC design. The goal of the project is to develop the automatic layout platform for capacitor-arrays including logic-ratio assignment by considering process variation, physical assignment and routing for physical-ratio, balanced assignment and routing by compensation. In this year, there are three topics to be further considered: 1. Studying the effects of systematic and random-uncorrelate variations, 2. Enhancing the algorithm of logic-ratio assignment, and 3. Enhancing the performance of physical assignment and routing-styles. This work is also to extend to explore the method of identification and extraction for the variation parameters and their characterization (modeling), which can be applied to the within-die capacitor-arrays and the dies on wafers. It is to achieve the reliability and quality of products in nanometer semiconductor technology, this project will provide that considers the random and systematic mismatches of the devices. Our system platform will be developed in Matlab by integrated with the simulation and design tools, like HSpice and Laker, in current design flow. The common circuits of Switched-Capacitor analog circuits are used to verify the developed platform. the
    Relation: 財團法人國家實驗研究院科技政策研究與資訊中心
    Appears in Collections:[電機工程學系] 研究計畫

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