應用於高畫質無線傳輸之低功耗、高性能之V頻段達靈頓架構收發機之研製;The Impplementations of Low Power Consumption and High Performance V-Band Darlington Transceiver for Wireless High Definition Digital Signal (Wireless Hd) Transmission

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题名:	應用於高畫質無線傳輸之低功耗、高性能之V頻段達靈頓架構收發機之研製;The Impplementations of Low Power Consumption and High Performance V-Band Darlington Transceiver for Wireless High Definition Digital Signal (Wireless Hd) Transmission
作者:	邱煥凱
贡献者:	國立中央大學電機工程學系
关键词:	電子電機工程;電信工程
日期:	2012-12-01
上传时间:	2014-03-17 14:19:23 (UTC+8)
出版者:	行政院國家科學委員會
摘要:	研究期間：10108~10207;This three-year project is primarily targeted to study the key components for V-band millimeter wave transceiver using Darlington pair technology. In the first year, we dedicate to design the Darlington pairs for each V-band functional circuit using TSMC 90-nm CMOS technology. The equivalent circuit analysis will be first derived, and the design criteria using Darlington pairs for LNA, VCO, and mixer circuits will be extensively investigated. The Darlington pair is demonstrated, especially in its power gain performance, to have better fT and fmax than those in the single transistor. Since the power gain is so treasure in mm-wave frequency, the proposed Darlington pair circuits provides much better design margin to implement the functional circuits, such as LNA, mixer, and VCO in mm-wave frequency regime. In the 2nd year project, we will study the phase lock loop (PLL) system for V-band operation. The on-chip antenna and band-pass filter will be also designed in the second year. In the 3rd year project, we will measure the designed circuits and devising the S-TFML (slow wave thin film micro-strip line) model for each V-band circuit. Besides, we also will start to integrate the transmitter, receiver and PLL into a compact size system-on-a-chip (SoC), respectively. The transceivers include a Darlington low noise amplifier (LNA), a drive amplifier (DA), a medium power amplifier (PA), two Darlington up/down mixers, a Darlington voltage control oscillator (VCO), a Darlington divider and phase-locked loop (PLL). The antenna system is combined with on-chip antenna array, switch and band-pass filter. The designed circuits are fabricated in TSMC 90-nm CMOS technology
關聯:	財團法人國家實驗研究院科技政策研究與資訊中心
显示于类别:	[電機工程學系] 研究計畫

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