研究期間：10208~10307;With the advent integrated circuit (IC) technology, there are two major trends in the future of IC designs. One trend is to design advanced system-on-chip (SOC) following the Moore's Law. Another trend is to design a system chip with the three-dimensional integration technology using through-silicon vias (TSVs), we call the system chip as 3D IC. Undoubted, memory is a key component in either the SOC or the 3D IC. Furthermore, memories in these two types of ICs usually represent a significant portion of the chip area. Therefore, efficient reliability and yield-enhancement techniques should be developed for the memories in SOCs and 3D ICs. In this three-year project, we will develop effective test, yield-enhancement, and reliability-enhancement techniques for variation-tolerance SRAMs, 3D RAMs, and heterogeneous memories. Also, we will develop effective reliability-enhancement techniques for 3D DRAMs. Finally, we will develop a reliability and yield-enhancement design automation platform for heterogeneous memories.