結合良率、可靠度與佈局考量的類比積體電路設計自動化與最佳化技術;Design Automation and Optimization for Analog Circuits with Yield, Reliability and Layout Consideration

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題名:	結合良率、可靠度與佈局考量的類比積體電路設計自動化與最佳化技術;Design Automation and Optimization for Analog Circuits with Yield, Reliability and Layout Consideration
作者:	劉建男
貢獻者:	國立中央大學電機工程學系
關鍵詞:	電子電機工程
日期:	2013-12-01
上傳時間:	2014-03-17 14:20:16 (UTC+8)
出版者:	行政院國家科學委員會
摘要:	研究期間：10208~10307;With nanometer semiconductor technology, the device size is continuously shrinking. Due to smaller device sizes, the parameter variations and aging effects have more impacts on the chip performance, yield and reliability. Therefore, how to consider the process variation and aging effects in early design stages has become a hot research direction in recent years. The DFY techniques for digital circuits have been studied for several years. However, for more sensitive analog circuits, no systematic CAD techniques are available now. Therefore, in this project, we will try to develop automatic yield-aware and reliability-aware optimization methodologies for analog circuits to help designers generate high-quality circuits in a short time. The process variation and aging effects are often not considered in traditional design automation algorithms. Without yield consideration, those optimization algorithms typically push the system performance to some corners that are vulnerable to parametric variation. In this project, there are two primary research directions to solve this issue. The first research direction is to include the yield and reliability considerations such that the synthesis engine can optimize them simultaneously. After preliminary studies, we will try to extend the synthesis algorithms to support complex analog circuits. Although synthesis tools can shorten the design time for new design projects, current synthesis algorithms often take too much time in large circuits. Therefore, the second research direction is to develop behavior-level yield enhancement techniques for existing analog circuits with the consideration of process variation and aging effects. They can reduce the required computation time to support complex analog circuits. Finally, we will try to consider the layout effects into the proposed algorithms to improve the accuracy of synthesis results. Those synthesis results will also be verified with real chip implementation results. Hope this yield-aware and reliability-aware design automation platform can save considerable design time for analog circuits and improve the overall yield of SOC designs.
關聯:	財團法人國家實驗研究院科技政策研究與資訊中心
顯示於類別:	[電機工程學系] 研究計畫

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