研究期間：10208~10307;his program is targeted to a system-on-a-chip (SoC) for K-band Wireless Sensor Network (WSN) application. Direct Conversion Receiver (DCR) architecture is chosen to meet the requirements of low power, compact size, low cost and the reduction of off-chip components. The chip set will be implemented by tsmcTM 90 nm or 180 nm CMOS Technologies. The development and verification in WSN will be extensively investigated in this three-year project. The transmitter with high efficiency, low power supply with high data rate is the goal in the first year. In the transmitter system, low power consumption and low phase noise oscillator, high quality factor (Q) resonator and active balun, low power supply power amplifier in switch mode are included. The K-band receiver is the goal in the second year. Each building block of the receiver is designed for low power and low noise specifications. The goal in the third year is to integrate each building block developed in the previous two years as a fully integated K-band WSN. The noise reduction, impedance matching, coupling effect and DC bias bypass issues need to consider in functional partition and layout design. Meanwhile, Slow Wave Thin Film Microstrip Line (S-TFML) structurte will be proposed to further minimize the chip size.
