在本篇論文中，我們將同時使用時鐘閘複製（gated-clock cloning）與正反器合併（flip-flop merging）技術，並將其融入全域擺置器（global placer）中，在擺置階段（in-placement）就開始進行時鐘網路的功率優化。利用調整標準元件（standard cell）、正反器和時鐘閘之間互相影響的力量（force），儘可能地多使用多位元正反器以及複製適當數量的時鐘閘，使得時鐘網路的動態功率消耗為最低。實驗結果顯示，我們提出的方法，可以讓時鐘網路的動態功率消耗，比起先前的研究再降低約49%。 ;Low power techniques in integrated circuit designs are more important because portable electric products are popular in recent years. According to the experimental results in , up to 70% of the dynamic power is dissipated by a clock network. If the power consumption of a clock network can be reduced, the total power consumption of the circuit can effectively get improvement.
Previous works mentioned that using clock gates and multi-bit flip-flops can effectively reduce the power consumption of a clock network. For optimizing the power consumption of a clock network, most of previous works only focus on using clock gates or multi-bit flip-flops in the placement stage, or simultaneously using clock gates and flip-flops in the post-placement stage. Therefore, both methods are hard to obtain better results.
In this thesis, we integrated gated-clock cloning and flip-flop merging techniques in our global placer. Clock gates and multi-bit flip-flops are used simultaneously to optimize the dynamic power of a clock network in the placement stage. As many as possible multi-bit flip-flops and a suitable number of clock gates are determined by the proposed algorithm. Experimental results showed that the proposed algorithms can reduce more than 49% dynamic power of a clock network than previous works.