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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/65739

    Title: 在擺置階段使用正反器合併與時鐘閘複製技術節約時鐘網路功耗;In-Placement Power Saving for a Clock Network with Flip-Flop Merging and Gated-Clock Cloning
    Authors: 陳正傑;Chen,Cheng-Chieh
    Contributors: 電機工程學系
    Keywords: 正反器合併;時鐘閘複製;多位元正反器;功率;Flip-flop merging;Gated-clock cloning;Multi-bit flip-flops;Power
    Date: 2014-07-24
    Issue Date: 2014-10-15 17:09:14 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 近年來因為可攜式電子產品的普及,低功率的積體電路設計技術也愈來愈重要。根據 [12] 的實驗結果指出,在整個積體電路中,時鐘網路(clock network)所占的動態功率(dynamic power)消耗百分比為最大,最高可以到達70%,因此如果能夠大量地減少時鐘網路的功率消耗,對電路的整體功率消耗也能有效地改善。

    在許多的相關文獻中提到使用時鐘閘(clock gate)和多位元正反器(multi-bit flip-flop)可以有效地節省時鐘網路的功率消耗。然而大部分的研究都只針對時鐘閘或多位元正反器其中之一進行時鐘網路的功率優化,或是同時考慮兩者但是卻在後擺置階段(post-placement)處理,因此效果並不夠好。

    在本篇論文中,我們將同時使用時鐘閘複製(gated-clock cloning)與正反器合併(flip-flop merging)技術,並將其融入全域擺置器(global placer)中,在擺置階段(in-placement)就開始進行時鐘網路的功率優化。利用調整標準元件(standard cell)、正反器和時鐘閘之間互相影響的力量(force),儘可能地多使用多位元正反器以及複製適當數量的時鐘閘,使得時鐘網路的動態功率消耗為最低。實驗結果顯示,我們提出的方法,可以讓時鐘網路的動態功率消耗,比起先前的研究再降低約49%。
    ;Low power techniques in integrated circuit designs are more important because portable electric products are popular in recent years. According to the experimental results in [12], up to 70% of the dynamic power is dissipated by a clock network. If the power consumption of a clock network can be reduced, the total power consumption of the circuit can effectively get improvement.

    Previous works mentioned that using clock gates and multi-bit flip-flops can effectively reduce the power consumption of a clock network. For optimizing the power consumption of a clock network, most of previous works only focus on using clock gates or multi-bit flip-flops in the placement stage, or simultaneously using clock gates and flip-flops in the post-placement stage. Therefore, both methods are hard to obtain better results.

    In this thesis, we integrated gated-clock cloning and flip-flop merging techniques in our global placer. Clock gates and multi-bit flip-flops are used simultaneously to optimize the dynamic power of a clock network in the placement stage. As many as possible multi-bit flip-flops and a suitable number of clock gates are determined by the proposed algorithm. Experimental results showed that the proposed algorithms can reduce more than 49% dynamic power of a clock network than previous works.
    Appears in Collections:[電機工程研究所] 博碩士論文

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